Samsung S3C6400X User Manual page 1109

IRDA
BLOCK DIAGRAM
INTERRUPT, DMA
MCLK(48MHz)
HRESETn
AHB BUS
TX FIFO
RAM
RX FIFO
RAM
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
38-2
Specifications and information herein are subject to change without notice.
MASTER_Control
CLK_GEN
LSR
ACREG
MDR
FCR
TX FIFO Control
THR
PLR
RX FIFO Control
RBR
M
Figure 38-1 Block Diagram
S3C6400X RISC MICROPROCESSOR
Iinterrupt Control
and payload length
store
IER
ICR
RXFLH RXFLL
TXFLH TXFLL
FIR Mod/Demodl
PLL
MOD
DEMOD
MIR Mod/Demodl
MOD DEMOD
MUX
IRSDBW
IRRX
IRTX