Samsung S3C6400X User Manual page 920

HSMMC CONTROLLER
This bit is set to 1 when SD Clock output is stable after writing to SD Clock
Enable in this register to 1. The SD Host Driver waits to issue command to start
until this bit is set to 1. (ROC)
'1' = Ready
'0' = Not Ready
SD Clock Enable
[2]
The Host Controller stops SDCLK when writing this bit to 0. SDCLK Frequency
Select can be changed when this bit is 0. Then, the Host Controller shall maintain
the same clock frequency until SDCLK is stopped (Stop at SDCLK=0). If the Card
Inserted in the Present State register is cleared, this bit will be cleared. (RW)
'1' = Enable
'0' = Disable
Internal Clock Stable
[1]
This bit is set to 1 when SD Clock is stable after writing to Internal Clock Enable
in this register to 1. The SD Host Driver shall wait to set SD Clock Enable until this
bit is set to 1.
Note: This is useful when using PLL for a clock oscillator that requires setup time.
(ROC)
'1' = Ready
'0' = Not Ready
Internal Clock Enable
[0]
This bit is set to 0 when the Host Driver is not using the Host Controller or the
Host Controller awaits a wakeup interrupt. The Host Controller must stop its
internal clock to go very low power state. Still, registers shall be able to be read and
written. Clock starts to oscillate when this bit is set to 1. When clock oscillation is
stable, the Host Controller can be set Internal Clock Stable in this register to 1.
This bit shall not affect card detection. (RW)
'1' = Oscillate
'0' = Stop
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
27-44
Specifications and information herein are subject to change without notice.
S3C6400X RISC MICROPROCESSOR
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