Samsung S3C6400X User Manual page 1023

UART
UART INTERRUPT MASK REGISTER
Interrupt mask register contains the information of the masked interrupt. If a specific bit is set to 1, interrupt
request signal to Interrupt Controller is not generated even though corresponding interrupt is generated. (Note
that even in such a case, the corresponding bit of UINTSPn register is set to 1). If the mask bit is 0, the interrupt
request can be serviced from the corresponding interrupt source
(Note that even in such a case, the corresponding bit of UINTSPn register is set to 1).
Register Address
UINTM0 0x7F005038
UINTM1 0x7F005438
UINTM2 0x7F005838
UINTM3 0x7F005C38
UINTMn
MODEM
TXD
ERROR
RXD
31-28
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
R/W
R/W Interrupt Mask Register for UART channel 0
R/W Interrupt Mask Register for UART channel 1
R/W Interrupt Mask Register for UART channel 2
R/W Interrupt Mask Register for UART channel 3
Bit
[3] Mask Modem interrupt.
[2] Mask Transmit interrupt.
[1] Mask Error interrupt.
[0] Mask Receive interrupt.
S3C6400 RISC MICROPROCESSOR
Description
Description
Reset Value
0x0
0x0
0x0
0x0
Initial State
0
0
0
0