Turbo Product Codec (Fast Option; Tpc Overview - Comtech EF Data CDM-570A Installation And Operation Manual

B.5

Turbo Product Codec (FAST Option)

Turbo coding is an FEC technique, developed within the last few years, which delivers significant
performance improvements compared to more traditional techniques. Two general classes of
Turbo Codes have been developed, Turbo Convolutional Codes (TCC), and Turbo Product
Codes (TPC, a block coding technique). Comtech EF Data has chosen to implement an FEC
codec based on TPC. A Turbo Product Code is a 2 or 3 dimensional array of block codes.
Encoding is relatively straightforward, but decoding is a very complex process requiring multiple
iterations of processing for maximum performance to be achieved.
Unlike the popular method of concatenating an RS codec with a primary FEC codec, Turbo
Product Coding is an entirely stand-alone method. It does not require the complex interleaving/
de-interleaving of the RS approach, and consequently, decoding delays are significantly reduced.
Furthermore, the traditional concatenated RS schemes exhibit a very pronounced threshold effect
– a small reduction in Eb/No can result in total loss of demod and decoder synchronization. TPC
does not suffer from this problem – the demod and decoder remain synchronized down to the
point where the output error rate becomes unusable. This is considered to be a particularly
advantageous characteristic in a fading environment. Typically, in QPSK, 8-PSK and 16-QAM
TPC modes the demod and decoder can remain synchronized 2 – 3 dB below the Viterbi/Reed-
Solomon or TCM cases.
B.5.1

TPC Overview

In the past few years there has been an unprecedented resurgence in interest in FEC technology.
The start of this new interest has its origins in the work done by Claude Berrou et al, and the 1993
landmark paper, Near Shannon Limit Error Correcting Coding and Decoding – Turbo Codes. FEC
is considered an essential component in all wireless and satellite communications in order to
reduce the power and bandwidth requirements for reliable data transmission.
Claude Shannon, considered by many to be the father of modern communications theory, first
established the concept of Channel Capacity in his 1948 paper A Mathematical Theory of
Communication. This places an absolute limit on how fast it is possible to transmit error-free data
within a channel of a given bandwidth, and with given noise conditions within that channel. He
concluded that it would only be possible to approach this limit through the use of source encoding
– what is familiar today as FEC.
Shannon postulated that if it were possible to store every possible message in the receiver,
finding the stored message that most closely matched the incoming message would yield an
optimum decoding method. However, for all but the shortest bit sequences, the memory required
for this, and the time taken to perform the comparisons, makes this approach impractical. For all
practical purposes, the memory requirement and the decoding latency become infinite.
For many years, there were few advances in the quest to approach the Shannon Limit. The
Viterbi algorithm heralded a major step forward, followed in the early 1990s by the concatenation
of a Viterbi decoder with Reed-Solomon hard-decision block codes. It remained clear, however,
that the Shannon Limit was still an elusive target.
Berrou's work on Turbo Codes showed, through the use of an ingeniously simple approach
(multiple, or iterative decoding passes) that it is possible to achieve performance close to the
Shannon Limit. Berrou's early work dealt exclusively with iteratively-decoded convolutional codes
(Turbo Convolutional Coding, or TCC), but in time the iterative approach was applied to a
particular class of block codes called Product Codes – hence Turbo Product Coding (TPC). TPC
exhibits inherently low decoding latency compared with TCC, and so is considered much more
desirable for 2-way, interactive satellite communications applications.
FEC (Forward Error Correction) Options
CDM-570A/570AL Satellite Modem with Optional Packet Processor
B–5
Revision 5
MN-CDM570A