Architecture
Figure 35-15. Clock Control on Video Input and Output with SDTV Encoding
Video Input Clock
(27 MHz)
Video Input Data [7:0]
Video Reference Clock
(27 MHz)
Video Output Clock
(27 MHz)
Video Output Data [7:0]
1780
Video Port Interface (VPIF)
On Chip
Video Port Interface
CLKIN0
DIN[7:0]
CLKIN2
CLKOUT2
DOUT[7:0]
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Memory
FIFO
Interface
Memory
FIFO
Interface
SPRUH82C – April 2013 – Revised September 2016
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