Table of Contents
Advertisement
www.ti.com
Digital I/O Characteristics (continued)
V
= 4.75 to 5.25 V; V
= 3.3 to 5 V T
CC
VIO
PARAMETER
Transition low-to-high delay
T
(1)
IDLY_H
time
Transition high-to-low delay
T
IDLY_L
(1)
time
R
Internal pulldown resistance
PD
R
Internal pullup resistance
PU
6.11 Oscillator Characteristics
V
= 4.75 to 5.25 V, T
= –40°C to +125°C (unless otherwise noted)
CC
A
PARAMETER
f
External oscillator frequency
OSC_E
f
Internal oscillator frequency
OSC_I
System-clock out-of-range
E
OSC
threshold
t
Device start-up time
POR
(1) Parameter specified by design
6.12 Output Data Interface Characteristics
Over operating free-air temperature range, V
PARAMETER
PARALLEL DIGITAL OUTPUT (ORD[11:0])
RATE
ORD_DA
Parallel-data output rate
TA
t
Parallel-data output update time
ORD_DATA
EMULATED ENCODER OUTPUT (OUTA, OUTB, OUTZ, OUTU, OUTV, OUTW, OUTU1, OUTV1, OUTW1)
OUTA and OUTB resolution in
ABZ
10BIT_RES
10-bit mode
OUTA and OUTB resolution in
ABZ
12BIT_REZ
12-bit mode
OUTZ resolution (10-bit mode or
ABZ
OUTZ
12-bit mode)
Maximum rotation supported by
ABZ
RPM
emulated encoder mode
Rise and fall times of emulated
t
ABZ
encoder outputs
ANALOG OUTPUT MONITOR
RES
Analog output DAC resolution
MON_DAC
V
Analog output-voltage range
MON_DAC
6.13 SPI Interface Timing Requirements
V
= 4.75 to 5.25 V, T
= –40°C to +125°C (unless otherwise noted)
CC
A
f
SPI clock (SCLK) frequency
SPI
t
High time: SCLK logic high time duration
whigh
t
Low time: SCLK logic low time duration
wlow
t
NCS setup time: Time delay between falling edge of NCS and rising edge of SCLK
su_cs
t
Hold time: Time between the falling edge of SCLK and rising edge of NCS
h_cs
t
Delay time: Time delay from falling edge of NCS to data valid at SDO
pd_soen
t
Delay time: Time delay from rising edge of NCS to SDO transition to tri-state
pd_sodis
t
SDI setup time: Setup time of SDI before the falling edge of SCLK
su_si
t
Hold time: Time between the falling edge of SCLK to SDI valid
h_si
t
Propagation delay from rising edge of SCLK to SDO
pd_so
t
SPI transfer inactive time (time between two transfers) during which NCS must remain high
w_cs
Copyright © 2015–2017, Texas Instruments Incorporated
= –40°C to +125°C (unless otherwise noted)
A
TEST CONDITIONS
V
= 5 V
PIN
NCS pin; V
= 0 V
PIN
TEST CONDITIONS
(1)
20-MHz XTAL; ECLKSEL = H
NPOR asserted
(1)
From VDD_UV = L
= 4.75 to 5.25 V, T
IN
TEST CONDITIONS
V
= 3.3 V; C
= 50 pF; SPI clock tolerance
VIO
SDO
= ± 10%
C
= 50 pF
SDO
Product Folder Links:
SLASE76E – NOVEMBER 2015 – REVISED AUGUST 2017
MIN
40
40
MIN
18.4
–30%
= –40°C to +125°C (unless otherwise noted).
A
MIN
0.5
MIN
55
55
55
55
15
15
200
Submit Documentation Feedback
PGA411-Q1
PGA411-Q1
TYP
MAX
UNIT
40
ns
40
ns
100
160
kΩ
100
160
kΩ
TYP
MAX
UNIT
20
MHz
20
21.6
MHz
40%
1.5
ms
TYP
MAX
UNIT
10
MHz
100
ns
256
pulses/rotation
1024
pulses/rotation
1
pulses/rotation
200 000
RPM
160
200
us
10
Bit
4.5
V
NOM
MAX
UNIT
8
MHz
ns
ns
ns
ns
55
ns
55
ns
ns
ns
45
ns
ns
13
Advertisement
Table of Contents
