Timing Specifications; Table 4-4. Signal Names Used In Timing Diagrams - National Instruments DAQ PCI-6023E User Manual

Timing Specifications

Name Type
STB* Input
IBF Output
© National Instruments Corporation
2. Using the following formula, calculate the largest possible load to
maintain a logic low level of 0.4 V and supply the maximum driving
current:
V = I * R R
L L
V = 0.4 V
I = 46 A + 10 A
Therefore:
R = 7.1 k
L
This resistor value, 7.1 k , provides a maximum of 0.4 V on the DIO line
at power up. You can substitute smaller resistor values to lower the voltage
or to provide a margin for V
smaller values will draw more current, leaving less drive current for other
circuitry connected to this line. The 7.1 k resistor reduces the amount of
logic high source current by 0.4 mA with a 2.8 V output.
(PCI-6025E Only)
This section lists the timing specifications for handshaking with your
PCI-6025E PC<0..7> lines. The handshaking lines STB* and IBF
synchronize input transfers. The handshaking lines OBF* and ACK*
synchronize output transfers. Table 4-4 describes signals appearing in the
handshaking diagrams.

Table 4-4. Signal Names Used in Timing Diagrams

Strobe Input—A low signal on this handshaking line loads data into
the input latch.
Input Buffer Full—A high signal on this handshaking line indicates
that data has been loaded into the input latch. A low signal indicates
the board is ready for more data. This is an input acknowledge
signal.
= V/I, where:
; Voltage across R
; 4.6 V across the 100 k pull-up resistor
and 10 A maximum leakage current
; 0.4 V/56 A
variations and other factors. However,
cc
Description
4-25
Chapter 4 Signal Connections
L
PCI-6023E/6024E/6025E User Manual