Sun Microsystems Blade 1500 Service, Diagnostics, And Troubleshooting Manual page 442

C.3.2.2 L1 Instruction Cache
32 KBytes
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Pseudo four-way set associative
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Physically indexed (goes through I-TLB), physically tagged (goes through I-TLB)
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Write invalidate
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32-byte line size, no sub-lines
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Data and tags are parity protected
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Not included in L2 cache. Is snooped in parallel with L2
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No flushing is required
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C.3.2.3 L1 Prefetch Cache
Used by software prefetch instruction and autonomous HW prefetch from L2
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2 KBytes
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Four-way set associative
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Physically indexed (goes through D-TLB), physically tagged (goes through D-
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TLB)
Write invalidate
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64-byte line size, two 32-byte sub lines
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Not included in L2 cache. Is snooped in parallel with L2
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No flushing is required
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C.3.2.4 L2 Data Cache
1 MByte
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Four-way set associative
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Physically indexed (goes through D-TLB), physically tagged (goes through D-
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TLB)
Write back, allocating
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64-byte line size
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Data is ECC protected, tag is parity protected
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L2 tag address able to cache 16 GB of local memory
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Required flushing for stable storing
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C-10 Sun Blade 1500 Service, Diagnostics, and Troubleshooting Manual • December 2004