Texas Instruments TMS320DM335 Manuals

Manuals and User Guides for Texas Instruments TMS320DM335. We have 1 Texas Instruments TMS320DM335 manual available for free PDF download: User Manual

Texas Instruments TMS320DM335 User Manual (172 pages)

Digital Media System-on-Chip DMSoC ARM Subsystem

Brand: Texas Instruments | Category: Single board computers | Size: 1 MB

Table of Contents
3
Preface
13
Introduction
16
Device Overview
16
Block Diagram
16
ARM Subsystem in DM335
17
Functional Block Diagram
17
ARM Subsystem Overview
18
Purpose of the ARM Subsystem
18
Components of the ARM Subsystem
18
References
19
ARM Subsystem Block Diagram
19
ARM Core
20
Introduction
20
Operating States/Modes
21
Processor Status Registers
21
Exceptions and Exception Vectors
22
The 16-BIS/32-BIS Concept
22
3.5.1 16-BIS/32-BIS Advantages
22
Exception Vector Table for ARM
22
Coprocessor 15 (CP15)
23
3.6.1 Addresses in an ARM926EJ-S System
23
Different Address Types in ARM System
23
3.6.2 Memory Management Unit
24
3.6.3 Caches and Write Buffer
24
Tightly Coupled Memory
26
ITCM/DTCM Memory Map
26
Embedded Trace Support
27
ITCM/DTCM Size Encoding
27
ETM Part Descriptions
27
Memory Mapping
29
Memory Map
29
4.1.1 ARM Internal Memories
30
4.1.2 External Memories
30
4.1.3 Peripherals
30
ARM Configuration Bus Access to Peripherals
31
Memory Interfaces Overview
33
4.2.1 Ddr2 Emif
33
4.2.2 External Memory Interface
33
Device Clocking
35
Overview
35
Clocking Architecture
36
Peripheral Clocking Considerations
37
5.2.1 Video Processing Back End Clocking
37
5.2.2 USB Clocking
37
PLL Controllers (Pllcs)
38
PLL Controller Module
38
Pllc1
39
PLLC1 Output Clocks
39
PLLC1 Configuration
40
PLLC2 Output Clocks
40
PLLC2 Configuration
41
Clock Ratio Change and Alignment with Go Operation
43
PLL and Reset Controller Module Instance Table
44
PLLC Registers
44
Peripheral ID Register (PID)
46
Peripheral ID Register (PID) Field Descriptions
46
PLL Control Register (PLLCTL)
47
PLL Control Register (PLLCTL) Field Descriptions
47
PLL Multiplier Control Register (PLLM)
48
PLL Multiplier Control Register (PLLM) Field Descriptions
48
PLL Pre-Divider Control Register (PREDIV)
49
PLL Pre-Divider Control (PREDIV) Field Descriptions
49
PLL Controller Divider 1 Register (PLLDIV1)
50
PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions
50
PLL Controller Divider 2 Register (PLLDIV2)
51
PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions
51
PLL Controller Divider 3 Register (PLLDIV3)
52
PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions
52
PLL Post-Divider Control Register (POSTDIV)
53
PLL Post-Divider Control (POSTDIV) Field Descriptions
53
Bypass Divider Register (BPDIV)
54
Bypass Divider Register (BPDIV) Field Descriptions
54
PLL Controller Command Register (PLLCMD)
55
PLL Controller Command Register (PLLCMD) Field Descriptions
55
PLL Controller Status Register (PLLSTAT)
56
PLL Controller Status (PLLSTAT) Field Descriptions
56
PLL Controller Clock Align Control Register (ALNCTL)
57
PLL Controller Clock Align Control (ALNCTL) Field Descriptions
57
PLLDIV Ratio Change Status (DCHANGE)
58
PLLDIV Ratio Change Status (DCHANGE) Field Descriptions
58
Clock Enable Control Register (CKEN)
59
Clock Enable Control Register (CKEN) Field Descriptions
59
Clock Status Register (CKSTAT)
60
Clock Status Register (CKSTAT) Field Descriptions
60
SYSCLK Status Register (SYSTAT)
61
SYSCLK Status Register (SYSTAT) Field Descriptions
61
PLL Controller Divider 4 Register (PLLDIV4)
62
PLL Controller Divider 4 Register (PLLDIV4) Field Descriptions
62
Power and Sleep Controller (PSC)
63
Power Domain and Module Topology
63
Module Configuration
65
7.3.2 Module States
66
Icepick Emulation Commands
68
PSC Interrupt Events
68
PSC Registers
71
Peripheral Revision and Class Information Register (PID)
72
Peripheral Revision and Class Information Register (PID) Field Descriptions
72
Interrupt Evaluation Register (INTEVAL)
73
Interrupt Evaluation Register (INTEVAL) Field Descriptions
73
Module Error Pending Register 0 (Mod 0 - 31) (MERRPR0)
74
Module Error Pending Register 0 (Mod 0 - 31) (MERRPR0) Field Descriptions
74
Module Error Pending Register 1 (Mod 32-41) (MERRPR1)
75
Module Error Pending Register 1 (Mod 32-41) (MERRPR1) Field Descriptions
75
Module Error Clear Register 0 (Mod 0-31) (MERRCR0)
76
Module Error Clear Register 0 (Mod 0-31) (MERRCR0) Field Descriptions
76
Module Error Clear Register 1 (Mod 32-41) (MERRCR1)
77
Module Error Clear Register 1 (Mod 32-41) (MERRCR1) Field Descriptions
77
Power Error Pending Register (PERRPR)
78
Power Error Pending Register (PERRPR) Field Descriptions
78
Power Error Clear Register (PERRCR)
79
Power Error Clear Register (PERRCR) Field Descriptions
79
External Power Control Pending Register (EPCPR)
80
External Power Control Pending Register (EPCPR) Field Descriptions
80
External Power Control Clear Register (EPCCR)
81
External Power Control Clear Register (EPCCR) Field Descriptions
81
Power Domain Transition Command Register (PTCMD)
82
Power Domain Transition Command Register (PTCMD) Field Descriptions
82
Power Domain Transition Status Register (PTSTAT)
83
Power Domain Transition Status Register (PTSTAT) Field Descriptions
83
Power Domain Status N Register (Pdstatn)
84
Power Domain Status N Register (Pdstatn) Field Descriptions
84
Power Domain Control N Register (Pdctln)
85
Power Domain Control N Register (Pdctln) Field Descriptions
85
Module Status N Register (Mdstatn)
86
Module Status N Register 0-32 (Mdstatn) Field Descriptions
86
Module Control N Register 0-41 (Mdctln)
87
Module Control N Register 0-51 (Mdctln) Field Descriptions
87
AINTC Interrupt Connections
88
AINTC Functional Diagram
90
Interrupt Entry Table
91
Immediate Interrupt Disable / Enable
92
Delayed Interrupt Disable
92
Interrupt Controller (INTC) Registers
93
Interrupt Status of INT[31:0] (if Mapped to FIQ)
94
Interrupt Status of INT[31:0] (if Mapped to FIQ) Field Descriptions
94
Interrupt Status of INT[63:32] (if Mapped to FIQ)
95
Interrupt Status of INT[63:32] (if Mapped to FIQ) Field Descriptions
95
Interrupt Status of INT[31:0] (if Mapped to IRQ)
96
Interrupt Status of INT[31:0] (if Mapped to IRQ) Field Descriptions
96
Interrupt Status of INT[31:0] (if Mapped to IRQ)
97
Interrupt Status of INT[31:0] (if Mapped to IRQ) Field Descriptions
97
Fast Interrupt Request Entry Address Register (FIQENTRY)
98
Fast Interrupt Request Entry Address Register (FIQENTRY) Field Descriptions
98
Interrupt Request Entry Address Register (IRQENTRY)
99
Interrupt Request Entry Address Register (IRQENTRY) Field Descriptions
99
Interrupt Enable Register 0 (EINT0)
100
Interrupt Enable Register 0 (EINT0) Field Descriptions
100
Interrupt Enable Register 1 (EINT1)
101
Interrupt Enable Register 1 (EINT1) Field Descriptions
101
Interrupt Operation Control Register (INTCTL)
102
Interrupt Operation Control Register (INTCTL) Field Descriptions
102
EABASE Field Descriptions
103
Interrupt Priority Register 0 (INTPRI0)
104
Interrupt Priority Register 0 (INTPRI0) Field Descriptions
104
Interrupt Priority Register 1 (INTPRI1)
105
Interrupt Priority Register 1 (INTPRI1) Field Descriptions
105
Interrupt Priority Register 2 (INTPRI2)
106
Interrupt Priority Register 2 (INTPRI2) Field Descriptions
106
Interrupt Priority Register 3 (INTPRI3)
107
Interrupt Priority Register 3 (INTPRI3) Field Descriptions
107
Interrupt Priority Register 4 (INTPRI4)
108
Interrupt Priority Register 4 (INTPRI4) Field Descriptions
108
Interrupt Priority Register 5 (INTPRI5)
109
Interrupt Priority Register 5 (INTPRI5) Field Descriptions
109
Interrupt Priority Register 6 (INTPRI6)
110
Interrupt Priority Register 6 (INTPRI6) Field Descriptions
110
Interrupt Priority Register 7 (INTPRI7)
111
Interrupt Priority Register 7 (INTPRI7) Field Descriptions
111
Device Configuration
112
Master Ids
115
Default Master Priorities
116
System Module (SYS) Registers
117
PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register
118
PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register Field Descriptions
118
PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register
120
PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register Field Descriptions
120
PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register
122
PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register Field Descriptions
122
PINMUX3 - Pin Mux 3 (Gio/Misc) Pin Mux Register Field Descriptions
124
PINMUX3 - Pin Mux 3 (Gio/Misc) Pin Mux Register
126
PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register
127
PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register Field Descriptions
127
BOOTCFG - Boot Configuration
128
BOOTCFG - Boot Configuration Field Descriptions
128
ARM_INTMUX - ARM Interrupt Mux Control Register
129
ARM_INTMUX - ARM Interrupt Mux Control Register Field Descriptions
129
EDMA_EVTMUX - EDMA Event Mux Control Register
130
EDMA_EVTMUX - EDMA Event Mux Control Register Field Descriptions
130
DDR_SLEW - DDR Slew
131
DDR_SLEW - DDR Slew Field Descriptions
131
CLKOUT - CLKOUT DIV/Out Control
132
CLKOUT - CLKOUT DIV/Out Control Field Descriptions
132
DEVICE_ID - Device ID
133
DEVICE_ID - Device ID Field Descriptions
133
VDAC_CONFIG - Video Dac Configuration
134
VDAC_CONFIG - Video Dac Configuration Field Descriptions
134
TIMER64_CTL - Timer64+ Input Control
135
TIMER64_CTL - Timer64+ Input Control Field Descriptions
135
USB_PHY_CTRL - USB PHY Control
136
USB_PHY_CTRL - USB PHY Control Field Descriptions
136
MISC - Miscellaneous Control
138
MSTPRI0 - Master Priorities 0
138
MISC - Miscellaneous Control Field Descriptions
138
Master Priorities 1(MSTPRI1) Register
139
Master Priorities 1 (MSTPRI1) Register Field Descriptions
139
VPSS_CLK_CTRL - VPSS Clock Mux Control
140
VPSS_CLK_CTRL - VPSS Clock Mux Control Field Descriptions
140
Deep Sleep Mode Configuration (DEEPSLEEP) Register
141
Deep Sleep Mode Configuration (DEEPSLEEP) Register Field Descriptions
141
DEBOUNCE[8] - De-Bounce for Gio[N] Input
142
DEBOUNCE[8] - De-Bounce for Gio[N] Input Field Descriptions
142
VTP IO Control Register (VTPIOCR)
143
VTPIOCR - VTP IO Control Field Descriptions
143
Reset Types
144
10.2 Reset Pins
144
Boot Modes Overview
150
Boot Mode Functional Block Diagram
151
NAND Boot Flow
152
NAND UBL Descriptor
153
UBL Signatures and Special Modes
153
NAND Boot Mode Flow Chart
156
ARM NAND ROM Boot Loader Example
157
Descriptor Search for ARM NAND Boot Mode
158
NAND Ids Supported
158
MMC/SD Boot Mode Overview
160
MMC/SD UBL Descriptor
161
MMC/SD UBL Signatures and Special Modes
161
MMC/SD Boot Mode Flow Chart
162
ARM MMC/SD ROM Boot Loader Example
163
Descriptor Search for ARM MMC/SD Boot Mode
164
UART Boot Mode Handshake
165
UART Data Sequences
166
Host Utility Timing
167
Host Utility Data Format
167
CRC32 Table Transfer
167
Power Management Features
168

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