Cmos Setting (Clrtc) (Jp1); Chassis Intruder (Chassis) (Jp2); Pin Header (Usb 56, 78) - Aaeon EMB-A50M User Manual

M i n i - I T X

2.7 CMOS Setting (CLRTC) (JP1)

JP1
1-2
2-3

2.8 CHASSIS INTRUDER (CHASSIS) (JP2)

JP2
3-4
OPEN

2.9 Pin Header (USB 56, 78)

Pin Signal
1 +5V
3 USBD1-
5 USBD1+
7 GND
9 GND
2.10 USB 3.0 Connector (USB 3_34)
Pin Signal
1 +5V_USB3_2_P1
2 U3_2_U3RXDN1
3 U3_2_U3RXDP1
4 GND
5 U3_2_U3TXDN1
6 U3_2_U3TXDP1
7 GND
8 U3_2_U2DN1
9 U3_2_U2DP1
10 N.C
Chapter 2 Quick Installation Guide
Function
Normal (Default)
Clear CMOS
Function
Normal
CHASSIS INTRUDER
2 - 14
E M B - A 5 0 M
Pin Signal
2 GND
4 GND
6 USBD2+
8 USBD2-
10 +5V
Pin Signal
11 +5V_USB3_2_P2
12 U3_2_U3RXDN2
13 U3_2_U3RXDP2
14 GND
15 U3_2_U3TXDN2
16 U3_2_U3TXDP2
17 GND
18 U3_2_U2DN2
19 U3_2_U2DP2
20 N.C