Casio QT-6600 Service Manual page 96

Causes of error occurrence
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(1) error no. 40: TLB address comparison results in address mismatch
(2) error no. 60: TLB entry is invalid
Description of phenomenon:
The CPU performs a conversion from logical address to physical address when
accessing the external memory.
TLB is what caches that information.
If an error occurs in the process of the caching, a general exception of the CPU occurs.
Possible causes:
A malfunction of the CPU, because this is an internal operation of the CPU.
(3) error no. 80: Initial page write exception
Description of phenomenon:
This exception occurs if the address conversion table of the above TLB is illegally
written.
Possible causes:
A malfunction of the CPU, because this is an internal operation of the CPU.
(4) error no. A0: TLB protection exception (read)
(5) error no. C0: TLB protection exception (write)
Description of phenomenon:
TLB is protected by setting access right. An access that violates the access right causes
one of these exceptions to occur.
Possible causes:
A malfunction of the CPU, because this is an internal operation of the CPU.
(6) error no. E0: CPU address error (read)
(7) error no. 100: CPU address error (write)
Description of phenomenon:
This exception occurs if an illegal address is accessed (read or written).
Possible causes:
• An illegal address is accessed by software (a software bug).
• The address to be accessed has changed due to insufficient charge of the backup
battery for RAM.
(8) error no. 180: Reservation instruction code exception
(9) error no. 1A0: Slot illegal instruction exception
Description of phenomenon:
These exceptions occur when an illegal instruction is performed.
Possible causes:
It is hard to think that this phenomenon is caused by software, because these errors
occur due to an internal operation of the CPU.
This phenomenon is apt to occur when backup of RAM is not performed normally and
the memory has been changed.
It is possible that the data in RAM has become illegal data.
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