Memory Placement Rules - IBM Power Systems E870 Technical Overview And Introduction

Draft Document for Review October 14, 2014 10:19 am
A detailed diagram of the CDIMMs available for the Power E870 and Power E880 can be
seen in Figure 2-12.
Figure 2-12 Short CDIMM and Tall CDIMM details
The Memory Buffer is a L4 cache and is built on eDRAM technology (same as the L3 cache),
which has a lower latency than regular SRAM. Each CDIMM has 16 MB of L4 cache and a
fully populated Power E870 server has 1 GB of L4 Cache while a fully populated Power E880
has 2 GB of L4 Cache. The L4 Cache performs several functions that have direct impact on
performance and bring a series of benefits for the Power E870 and Power E880:
Reduces energy consumption by reducing the number of memory requests.
Increases memory write performance by acting as a cache and by grouping several
random writes into larger transactions.
Partial write operations that target the same cache block are gathered within the L4 cache
before being written to memory, becoming a single write operation.
Reduces latency on memory access. Memory access for cached blocks has up to 55%
lower latency than non-cached blocks.

2.3.2 Memory placement rules

For the Power E870 and Power E880, each memory feature code provides four CDIMMs.
Therefore a maximum of 8 memory feature codes per system node are allowed in order to fill
all the 32 DDR3 CDIMM slots.
All the memory CDIMMs are capable of capacity upgrade on demand and must have a
minimum of 50% of its physical capacity activated. For example, the minimum installed
Chapter 2. Architecture and technical overview
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