Level 4 Cache And Memory Buffer - IBM Power Systems E870 Technical Overview And Introduction

Draft Document for Review October 14, 2014 10:19 am
No off-chip driver or receivers
Removing drivers or receivers from the L3 access path lowers interface requirements,
conserves energy, and lowers latency.
Small physical footprint
The performance of eDRAM when implemented on-chip is similar to conventional SRAM
but requires far less physical space. IBM on-chip eDRAM uses only a third of the
components that conventional SRAM uses, which has a minimum of six transistors to
implement a 1-bit memory cell.
Low energy consumption
The on-chip eDRAM uses only 20% of the standby power of SRAM.

2.2.6 Level 4 cache and memory buffer

POWER8 processor-based systems introduce an additional level of memory hierarchy. The
Level 4 (L4) cache is implemented together with the memory buffer in the Custom DIMM
(CDIMM). Each memory buffer contains 16 MB of L4 cache. Figure 2-10 shows a picture of
the memory buffer, where you can see the 16 MB L4 cache, and processor links and memory
interfaces.
Figure 2-10 Memory buffer chip
Table 2-3 shows a comparison of the different levels of cache in the POWER7, POWER7+,
and POWER8 processors.
Table 2-3 POWER8 cache hierarchy
Cache
L1 instruction cache:
Capacity/associativity
L1 data cache:
Capacity/associativity
bandwidth
POWER7
32 KB, 4-way
32 KB, 8-way
Two 16 B reads or
one 16 B writes per cycle
POWER7+
32 KB, 4-way
32 KB, 8-way
Two 16 B reads or
one 16 B writes per cycle
Chapter 2. Architecture and technical overview
5137ch02.fm
POWER8
32 KB, 8-way
64 KB, 8-way
Two 16 B reads or
one 16 B writes per cycle
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