Sharp UP-3301 Service Manual page 61

6. Pseudo SRAM (Standard)
The device is a TOSHIBA 4MB SRAM (TC51V8512AFT 512K x 8bit)
with access time of 120ns.
6-1. CPU interface
The figure below shows a typical pseudo SRAM interface in the UP-
3301.
ISP2032
Odd side PSRAM
/OWR
/WR
/PCE1_O
/CE
/W3SWP
/RD
SD7~SD0
EVEN side PSRAM
SD7~SD0
/WR /HWR
/PCE1_E
/CE
/OE . /REFSH
/PSREF
/RESET
/PSRFO
ISP
2032
/RASPN12
6-2. Pseudo SRAM address
The standard pseudo SRAM is decoded as follows by the RASPN1 signal.
1 700000h ~ 7FFFFFh
The base signal is 2MB. Thus, it wraparounds with 600000H ~ 6FFFFFH
1MB.
The pseudo SRAM consists of 1 chip for respective even and odd num-
ber addresses. Both of word and byte access from CPU are available.
7. NOR-type flash memory
The NOR-type flash memory device is Sharp's LH28F016SU flash
memory which consists of 512 K words x 16 or 1 MB x 8, with 16 blocks
of 64 KB.
7-1. CPU interface
The figure below shows a typical interface for the LH28F016SU of the
UP-3301 system.
DATA
ADDRESS
HWR-
H8/510
RD-
FYPON
PORT64
NORDY
PORT63
RESET-
MPCA8
FROS1-
/LWR
/HWR
A0
/AS
Gate Array
/RESET
RASPN1
D7~D0
D15~D8
/AS
/RESET
RASPN1E
RASPN1
A0
RASPN1
or
RASPN2
Fig. 8
5V
DQ0 ~ DQ15 VCC
VPP
A0 ~ A21
WE#
OE#
LH28F
WP#
016SUT
RY/BY#
RP#
/IPLON0
BYTE#
CE0#
3/5#
CE1#
GND
Fig. 9
UP-3301US CIRCUIT DESCRIPTION
7-2. Device control
After resetting, the device automatically enters the array read mode and
perform the same action as the usual ROM, thus requiring no special
consideration when reading data.
Data can be written at high speed by using the page buffer.
8. SSP control
The UP-3301 uses flash memory in the place of a EPROM, so it is pos-
sible to rewrite the contents of the flash memory when changing the
program. However, since the existing MPCA8, it is also possible to use
the conventional SSP.
8-1. Operation
Like the MPCA7, the MPCA8 adopts the break address register com-
parison method for detecting addresses. The operation of this method
is briefly explained below.
The gate array always compares the break address register (BAR) built
in the gate array, with the address bus to monitor the address bus.
If both agree, the gate array outputs the NMI signal to the CPU, which in
turn shifts from normal handling to exception handling.
In both the MPCA7 and the MPCA8, SSP is achieved by the above
operation.
The setting of the break address register (BAR) is directly written in the
addresses from FFFF00h to FFFFFFh.
9. Interrupt control
There are roughly two types of interrupts:
• Internal interrupts: Controlled inside the CPU
• External interrupts: Input into the CPU from outside
9-1. Internal interrupts
Device interrupts built in the CPU are used for the following applications:
Event factor
SC11 Interrupt source as IR channel
SC12 Not used (SC1 is used for CKDC interface.)
FRT1 (ICI) INTMCR ~ MCR interrupt (to FT11 terminal)
(OCRA)
(OCRB)
(OVF)
FRT2 (ICI) Standard SHEN event (for CKDC)
(OCRA) Simple IRC timer event
(OCRB) RS232 timer event
(OVF) System timer (53 ms)
TMR (CMA)
(CMB)
(OVF)
WDT (OVF) Drawer open timer
A/D Not used
NMI SSP request
9-2. External interrupts
The following types of external interrupts are available:
• NMI (SSP)
• IRQ0 (Standard I/O interrupt)
• IRQ1 (RS232 interrupt)
• IRQ2 (Used as SCK terminal)
• IRQ3 (Used as SCK terminal)
– 59 –
Table 8
Application