Sharp UP-3301 Service Manual page 53

6. INTERFACE WITH HOST CPU
1) SIGNAL LINES
The following signal lines are required for the interface with the host CPU.
Signal name
A0~A11
D0~D7
/RD
/WR
/DPCS
/LRES
/INTSR
/INTSW
A13~A15
Vcc
GND
Note: Signals prefixed with a slash "/" are active in low level.
Cautions to be taken when designing the host side
1. It is preferable that /LRES signal to be input into the board can also
be controlled by software.
2. The access timing satisfies the dual-port SRAM specification.
• Timing Waveform of Read Cycle No. 1, Either Side
t
ADDRESS
(5)
t
AA
t
OH
DATA PREVIOUS DATA VALID
OUT
• Timing Waveform of Read Cycle No. 2, Either Side
t
ACE
CE
t
AOE
OE
(1)
t
LZ
DATA
OUT
(1)
t
LZ
t
PU
ICC
50%
CURRENT
I
SB
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH.
4. The start of valid data depends on which timing becomes effective,
tAOE, tACE or tAA
5. tAA is for RAM Address Access and tSAA for is Semaphore
Address Access.
I/O Description
I Address Bus from host CPU
I/O Data Bus from host CPU
I Read signal from host CPU
I Write signal from host CPU
I Chip select from host CPU
I Rest signal for this board from host CPU
O Data read end interrupt from board CPU
O Data write end interrupt from board CPU
I Address bus from host CPU (for decode)
Power (+5V)
GND
(1,2,4)
RC
t
OH
DATA VALID
(1,3)
(4) t (2)
HZ
(2)
t
HZ
(4)
VALID DATA
t
PD
50%
UP-3301US CIRCUIT DESCRIPTION
Connected to
Board CPU
• Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
ADDRESS
(6)
t
AS
OE
CE
R/W
t
(7)
t
LZ
DATA (4)
OUT
DATA
IN
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE =VIL and R/
W = VIL.
3. tWR is measured from the earlier of CE or R/W going to VIH to the
end-of-write cycle.
4. During this period, the I/O pins are in the output state, and the input
signals must not be applied.
5. If the CE = VIL transition occurs simultaneously with or after the R/
W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted
last.
7. This parameter is guaranteed by device characterization, but is not
production tested. Transition is measured m500mV from the steady
state with the Output Test Load (Figure 2).
8. If OE = VIL during a R/W controlled write cycle, the write pulse
width must be the larger of tWP or (tWZ + tDW) to allow the I/O driv-
ers to turn off data to be placed on the bus for the required tDW. If
OE = VIH during an R/W controlled write cycle, this requirement
does not apply and the write pulse can be as short as the specified
tWP.
– 51 –
Connection pin
DP-RAM A0R~A11R
DP-RAM D0R~D7R
DP-RAM /OER
DP-RAM R/WR
DP-RAM /CER
/RES
LOGIC
LOGIC
LOGIC
,
t
WC
(3)
t t
AW WR
(2)
t
WP
(7)
WZ
t
OW
t
DH
t
DW
(1,5,8)
t (7)
HZ
(7)
t
HZ
(4)