Sharp UP-3301 Service Manual page 47

Pin
Name UP-3301
NO.
132 TRNDTC TXD3
133 /DTRC /DTR3
134 /RTSC /RTS3
135 RCVDTC RCVDT3
136 /CTSC GND
137 /DSRC /DSR3
138 TRNRDYC TRNRDY3
139 RCVRDYC RCVRDY3
140 TRNEMPC TRNEMP3
141 SYCBKC NC
142 VCC VCC
143 GND GND
144 /CSD VCC
145 TRNDTD NC
146 /DTRD NC
147 /RTSD NC
148 RCVDTD GND
149 /CTSD GND
150 /DSRD GND
151 TRNRDYD NC
152 RCVRDYD NC
153 TRNEMPD NC
154 SYCBKD NC
155 /WIN /WRH
156 /RIN /RDH
157 RSLCT0 AH0
158 RSLCT1 AH1
159 RST RES USART
160 MCLK CLK USART
I TTL input
ID TTL input with pull down
IS TTL Schmidt input
ISU TTL Schmidt input with pull up
IO TTL I/O
3S 3-state Buffer (6mA)
ON6 Open drain (6mA)
I/O Description
O RS-232 transmission data
signal
O RS-232 data terminal ready
signal
O USART_C request to send
IS RS-232 reception data sig-
nal
IS GND
IS RS-232 data set ready sig-
nal
O RS-232 data transmission
enable signal
O RS-232 data reception
enable signal
O RS-232 transmission buffer
empty signal
IO NC
+5V
GND
IS USART_D chip select
O NC
O NC
O NC
IS GND
IS GND
IS GND
O NC
O NC
O NC
IO NC
I Write signal
I Read signal
I Address bus
I Address bus
IS Reset signal
I,
UP-3301US CIRCUIT DESCRIPTION
2-4. TCP/IP Interface
1. GENERAL DESCRIPTION
The Ethernet control supports the TCP/IP protocol.
2. BLOCK DIAGRAM
/INTSR
CN LOGIC
/INTSW
/DPCS,
/WR,/RD
Address
Dual-Port
Bus
RAM
4k byte
Data Bus
/CS3
LAN Cnt.
RJ-45
(8bit-Bus)
*When writing data into FLASH, switch /CS0to EP-ROM and /CS3 to
FLASH Memory.
3. CONFIGURATION
1 CPU : [HitachiSH-2 Series SH7014 (20MHz)] 1 1 1
External memory spaces, CS0 - CS3 and the DRAM space are pro-
vided. This board assigns FLASH Memory to CS0, SRAM to CS1, dual-
port SRAM to CS2, and LAN controller to CS3.
2 LAN Controller : [RealtekRTL8019AS (20MHz)] 2
2 2
The LAN controller is assigned to the CS space.
Because of the pseudo ISA connection, each register is assigned to
addresses of H00C00300 and after.
3 ROM (FLASH Memory) : [SharpLH28F004BVT(4Mbits)] 3 3 3
<Access Time = 90ns>
The ROM (FLASH Memory) is assigned to CS0 space.
Data is written onto FLASH Memory from UV-EPROM by switching the
CSO space to UV-EPROM and the CS3 space to FALSH Memory.
The MAC Address is written on FLASH Memory.
• The company code is assigned to "08001FH".
• The serial number and adjustment byte are stored in an area of 4
bytes from the address H'0007C000.
4 4 4 4 RAM : [S-RAM 1Mbits] <Access Time=70ns>
Assigned to the CS1 space.
[IDT Dual-Port SRAM IDT7134] <Access Time=55ns>
Assigned to the CS2 space.
The IDT7134 does not have any busy signal, access to the same
address from both sides is inhibited.
5 5 5 5 Pulse Trans : [Pulse78Z034]
Is used for the 10Base-T standard and has a choke coil built in at the
output side.
– 45 –
10MHz
/CS0
/INTHR
/CS1
/INTHW
CPU
/CS2
(SH-2)
/CS3
/CS1
/HWACK
/HRACK
LD0~LD7
/SWRQ
/SRRQ
SRAM
128k byte
LA0~LA18
/CS0
/CS2
LD0~LD7 LD0~LD7
FLASH
512k byte
LA0~LA11 LA0~LA18
/CS0
LD0~LD7 LD0~LD7
EP-ROM
(Writing in
to FLASH)
512k byte
LA0~LA19 LA0~LA18