Sharp UP-3301 Service Manual page 49

Watchdog Timer (WDT) (One Channel):
• Watchdog timer or interval timer
• A count overflow can generate an internal reset, external signal, or
interrupt
Serial Communication Interface (SCI) (Two Channels):
(Per Channel):
• Asynchronous or clock-synchronous mode is selectable
• Can transmit and receive simultaneously (full duplex)
• On-chip dedicated baud rate generator
• Multiprocessor communication function
I/O Ports:
• SH7014
– Input/output: 35
– Input: 8
– Total: 43
A/D Converter:
• 10 bits 8 channels
• The SH7014 has a high-speed A/D converter.
On-Chip Memory:
• ROM
– SH7014: ROMless
• RAM: SH7014: 3 kbytes (1 kbyte when cache is used)
Operating Modes:
• Operating modes
– Non-extended ROM mode
• Processing states
– Program execution state
– Exception processing state
• Power-down modes
– Sleep mode
– Software standby mode
Clock Pulse Generator (CPG):
• On-chip clock pulse generator
– On-chip clock-doubling PLL circuit
1)-2. Block Diagram
Figure 1. is a block diagram of the SH7014.
RES
WDTOVR
MD3
MD2
MD1
MD0
NMI
EXTAL
XTAL
PLLVCC
PLLCAP
PLLVSS
V
CC
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
AV
CC
AV
SS
: Peripheral address bus
: Peripheral data bus
: Internal address bus
: Internal upper data bus
: Internal lower data bus
1)-3. Pin Arrangement and Pin Functions
1)-3-1. Pin Arrangment
Figure 2. shows the pin arrangement for the SH7014 (top view).
PE0/TIOC0A/DREQ0 85
PE1/TIOC0B/DRAK0 86
PE2/TIOC0C/DREQ1 87
PE3/TIOC0D/DRAK1 88
PE4/TIOC1A 89
V 90
SS
91
PF0/AN0
PF1/AN1 92
93
PF2/AN2
PF3/AN3 94
95
PF4/AN4
PF5/AN5 96
AV 97
SS
PF6/AN6 98
PF7/AN7 99
AV 100
CC
V 101
SS
PE5/TIOC1B 102
V 103
CC
PE6/TIOC2A 104
PE7/TIOC2B 105
PE8 106
PE9 107
108
PE10
V 109
SS
PE11 110
PE12 111
PB13 112
Figure 2. SH7014 Pin Arrangement (QFP-112 Top View)
UP-3301US CIRCUIT DESCRIPTION
– 47 –
RAM (3 kB)/
cache (1 kB)
CPU
Direct memory
access controller
Interrupt
Bus state controller
controller
Serial communi-
Multifunction timer/
cation interface
pulse unit
(• 2 channels)
Watch-
A/D
Compare match
dog
converter
timer (• 2 channels)
timer
Figure 1. Block Diagram of the SH7014
QFP-112
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
56 D12
V
55
SS
54 D13
53
D14
52 D15
51
PA0/RXD0
50 PA1/TXD0
49 PA2/SCK0/DREQ0/IRQ0
48
PA3/RXD1
47 PA4/TXD1
46
PA5/SCK1/DREQ1/IRQ1
45 PA6/TCLKA/CS2
44 PA7/TCLKB/CS3
43 PA8/TCLKC/IRQ2
42 PA9/TCLKD/IRQ3
41 CS0
40 CS1
V
39 SS
38
WRL
V CC
37
36 WRH
35 WDTOVF
34 RD
V
33
SS
32
PB9/IRQ7/A21
31 PB8/IRQ6/A20/WAIT
30 PB7/A19
29 PB6/A18