Serial Ports - FabiaTech FX5634 Fanless Series User Manual

FabiaTech Corporation

Serial Ports

The ACEs (Asynchronous Communication Elements ACE1 to ACE2) are used to
convert parallel data to a serial format on the transmit side and convert serial data
to parallel on the receiver side. The serial format, in order of transmission and
reception, is a start bit, followed by five to eight data bits, a parity bit (if
programmed) and one, one and half (five-bit format only) or two stop bits. The
ACEs are capable of handling divisors of 1 to 65535, and produce a 16x clock for
driving the internal transmitter logic.
Provisions are also included to use this 16x clock to drive the receiver logic, also
included in the ACE a completed MODEM control capability, and a processor
interrupt system that may be software tailored to the computing time required to
handle the communications link.
The following table is a summary of each ACE accessible register
DLAB Port Address
0 Base + 0
0 Base + 1
X Base + 2
X Base + 3
X Base + 4
X Base + 5
X Base + 6
X Base + 7
1 Base + 0
1 Base + 1
Receiver Buffer Register (RBR)
Bit 0-7: Received data byte (Read Only)
Transmitter Holding Register (THR)
Bit 0-7: Transmitter holding data byte (Write Only)
Interrupt Enable Register (IER)
Bit 0: Enable Received Data Available Interrupt (ERBFI)
Register
Receiver buffer (read)
Transmitter holding register (write)
Interrupt enable
Interrupt identification (read only)
Line control
MODEM control
Line status
MODEM status
Scratched register
Divisor latch (least significant byte)
Divisor latch (most significant byte)
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