Chipset Features Setup - DFI P5BTX/L User Manual

3.1.3 Chipset Features Setup

Auto Configuration
DRAM Timing
DRAM Leadoff Timing
DRAM Read Burst (EDO/FP)
DRAM Write Burst Timing
Fast EDO Lead Off
Refresh RAS# Assertion
Fast RAS To CAS Delay
DRAM Page Idle Timer
DRAM Enhanced Paging
Fast MA to RAS# Delay
SDRAM (CAS Lat/RAS-to-CAS)
SDRAM Loading
System BIOS Cacheable
Video BIOS Cacheable
8 Bit I/O Recovery Time
16 Bit I/O Recovery Time
Memory Hole At 15M-16M
PCI 2.1 Compliance
PCI Concurrency
The settings on the screen are for reference only. Your version may not be
identical to this one.
This section gives you functions to configure the system based on the
specific features of the chipset. The chipset manages bus speeds and
access to system memory resources. It also coordinates
communications between the conventional ISA bus and the PCI bus.
These items should not be altered unless necessary. Depending on your
add-in boards, you may not or should not enable some of those
features. The default settings have been chosen because they provide
the best operating conditions for your system. The only time you might
consider making any changes would be if you discovered some incom-
patibility or that data was being lost while using your system.
Note:
The " SDRAM (CAS Lat/RAS-to-CAS)" field will appear only if the
system board is installed with DIM modules.
SDRAM Loading
This field must be set according to the memory size of the DIMM
installed in one of the DIMM socket.
Light 16MB DIMM
Middle 32MB DIMM
Heavy 64MB DIMM
Award BIOS Setup Utility
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
: Enabled Mem. Drive Str. (MA/RAS) : 16mA/16mA
: Normal
: 11/7/4
: x333/x444
: x444
: Disabled
: 5 Clks
: 2
: 6 Clks
: Enabled
: 2 Clks
: 3/3
: Light
: Disabled
: Disabled
ESC : Quit
: 4
F1 : Help
: 2
F5 : Old Values
: Disabled
: Disabled
F6 : Load Fail-Safe Settings
: Enabled
F7 : Load Optimal Settings
3
↑ ↓ → ←
: Select Item
PU/PD/+/- : Modify
(Shift) F2 : Color
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