Advantech PCE-3028 User Manual page 12

Lga1150 intel xeon, core i7/i5/i3/celeron/pentium picmg 1.3 half-size system host board with vga / dvi-d /ddr3 / sata3.0 / usb3.0 / dual gbe
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B.8
B.9
B.10
B.11
B.12
B.13
B.14
B.15
B.16
B.17
B.18
B.19
B.20
C.1
C.2
C.3
PCE-3028/4128 User Manual
Table B.7: CPU Fan Power Connector (CPUFAN1).................. 87
Reset Connector (FP1) ........................................................................... 88
Table B.8: Reset Connector (FP1 / RESET) ............................. 88
Hi-definition Audio Link Connector (HDAUD1) ....................................... 88
Table B.9: Hi-definition Audio Link Connector (HDAUD1)......... 88
LAN1 and LAN2 LED Connector (LANLED1) ......................................... 89
Table B.10:LAN1 and LAN2 LED Connector (LANLED1) .......... 89
GPIO Header (GPIO1)............................................................................ 89
Table B.11:GPIO Header (GPIO1) ............................................. 89
JWDT1 and JOBS1................................................................................. 90
Table B.12:JWDT1 and JOBS1 .................................................. 90
JCASE1 .................................................................................................. 90
Table B.13:JCASE1.................................................................... 90
LPC1 ....................................................................................................... 91
Table B.14:LPC1 ........................................................................ 91
PWR1...................................................................................................... 91
Table B.15:PWR1 ....................................................................... 91
DVI1 & DVI2............................................................................................ 92
Table B.16:DVI1 ......................................................................... 92
Fixed I/O Ranges Decoded by Intel PCH ............................................... 93
Table B.17:Fixed I/O Ranges Decoded by PCH......................... 93
System I/O Ports..................................................................................... 94
Table B.18:System I/O Ports ...................................................... 94
Interrupt Assignments ............................................................................. 95
Table B.19:Interrupt Assignments .............................................. 95
1 MB Memory Map.................................................................................. 95
Table B.20:1 MB memory map ................................................... 95
Supported GPIO Register ....................................................................... 98
GPIO Registers....................................................................................... 98
GPIO Example Program-1 ...................................................................... 98
xii
.................... 97

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