9.5.3
Ethernet MAC
All of these signals use VCCFPIO signalling levels. The VCCO selected by the jumper on the XRC-II/XPL
Bank
9.5.4
RS232
Bank
Page 23 of 29
should match the IOSTANDARD for these pins.
FPGA
Pin
1
H20
1
G20
1
F15
1
E15
1
C19
0
G22
0
F22
1
D19
0
E28
0
F28
0
C29
0
C28
0
J22
0
K22
0
L27
0
K27
1
E13
1
F13
1
K13
1
J13
O-PD
O-ST
Output with 25R source resistor
FPGA
Pin
0
C30
0
D30
0
M26
0
M25
The header pin-out is show below.
Signal
GND
GND
POL
GND
GND
XRM-ETH
Samtec
MAC Signal
62
64
66
68
90
97
99
92
94
96
98
100
102
104
106
107
18
20
26
28
Key
I
Input
O
Output
Output with 2K pulldown
XRM-ETH
Samtec
J4 Header
122
124
126
128
Pin
Samtec
2
1
4
3
6
5
8
7
10
9
ADM-XP
Comment
RXC
O-ST
TXC
O-ST
PD
I
TXER
I
RXDV
O-PD
RXD3
O-PD
RXD2
O-PD
RXD1
O-PD
RXD0
O-PD
TXEN
I
TXD0
I
TXD1
I
TXD2
I
TXD3
I
COL
O-PD
CRS
O-PD
MDC
I-PU
MDIO
IO-PU
RST_N
I-PU
RXER
O
Signal
1
TX0
3
RX0
7
TX1
9
RX1
Signal
TX0
RX0
NC
TX1
RX1
ADM-XR-IIPro User Manual
User Manual
Version 0.2
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