Alpha Data ADM-XRC-II Pro Hardware Manual page 11

within the V2Pro device and the allocation of the MGT resources on the board the MGT's are currently limited
to 2.5GBps operation using the REFCLK input to the transceivers.
The MCLK signal is input to the FPGA to provide a user clock of between 10 and 200MHz, single ended. The
local bus uses LCLK to synchronize transfers between the bridge and the target and is derived from MCLK by
a divide by 2 in the ICS307. Although the clocks are related, phase is not guaranteed.
A summary of the clock pins is shown in the table below.
Bank VCCO
0 JP1 select
0 JP1 select
0 JP1 select
0 JP1 select
1 JP1 select
1 JP1 select
1 JP1 select
1 JP1 select
4 2.5V
4 2.5V
4 2.5V
4 2.5V
2 2.5V
2 2.5V
2 2.5V
2 2.5V
5 2.5V
5 2.5V
5 2.5V
5 2.5V
If required, XRM related clocks should be terminated on the XRM itself. No terminations are provided on the
XP main board.
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GCLK Pin
7P K22
6S J22
5P F22
4S G22
0S K21
1P J21
2S F21
3P G21
0P AT21
1S AU21
2P AP21
3S AN21
- AB12
- AA12
- AA10
- AA9
6P AU22
7S AT22
4P AN22
5S AP22
Signal
IO_74N_0/GCLK7P
IO_74P_0/GCLK6S
IO_75N_0/GCLK5P
IO_75P_0/GCLK4S
IO_74P_1/GCLK0S
IO_74N_1/GCLK1P
IO_75P_1/GCLK2S
IO_75N_1/GCLK3P
LCLK
MCLK
DDR2_clk
DDR1_clk
DDR1_clk
DDR1_clkb
DDR2_clk
DDR2_clkb
MGT_clk
MGT_clkb
PN4 fpga_P3
PN4 fpga_N3
ADM-XP User Manual
Description
User clocks to / from XRM
Local Bus Clock :-
MCLK divided by 2
User programmable up to
200MHz. Default is 66MHz
Clock feedback DDR DRAM 1
Clock feedback DDR DRAM 0
Used for clock forwarding of
DDR clock outputs
Clock for the MGTs
PN4 IO clocks
ADM-XR-IIPro User Manual
Version 0.2