Ddr2 Ssram - Alpha Data ADM-XRC-II Pro Hardware Manual

5.4 DDR2 SSRAM

The XP supports four independent banks of CIO DDR2 SSRAM memory. The devices fitted are Samsung
512K *36 (K7I163684-FC16) parts or a functional equivalent. As an upgrade option 1Mx36 (K7I323684-FC16)
devices can also be fitted.
DDR2 SSRAM Bank 0
Add0[0:21]
Bwe0[0:3]
DDR2
Cclk0/Cclkb0
SSRAM
Kclk0/Kclkb0
Dq0[0:31]
DDR2 SSRAM Bank1
Add1[0:21]
Bwe1[0:3]
DDR2
Cclk1/Cclkb1
SSRAM
Kclk1/Kclkb1
Dq1[0:31]
The pins required for each SSRAM controller bank are listed below.
ZBTx_ad[0:21]
ZBTx_dq[0:31]
ZBTx_rw
ZBTx_bwe{0..3]
ZBTx_nld
ZBTx_Cclk/ZBTx_nCclk
ZBTx_Kclk/ZBTx_nKclk
ZBTx_DOFF
The SSRAM pins should be configured for HSTL_II_18 operation
The SSRAM clock Cclks and Kclks are intended to be used with clock-forwarding implemented in a DDR IOB
with a DCM used to adjust for SSRAM clock to output delays on the data input path to the FPGA.
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Bank 6
VCCO=1.8V
Name
Bank 7
VCCO=1.8V
2VP70 / 2VP100
FF1704
FPGA Pin Type
Output
Bidir
Output
Output
Output
Output
Output
Output
ADM-XP
DDR2 SSRAM Bank 2
Add0[0:21]
Bwe0[0:3]
Cclk0/Cclkb0
Kclk0/Kclkb0
Dq0[0:31]
DDR2 SSRAM Bank 3
Add0[0:21]
Bwe0[0:3]
Cclk0/Cclkb0
Kclk0/Kclkb0
Dq0[0:31]
Description
Address bus
Data bus
Read(1) / Write(0)
Byte enables for writes
Initiates a transaction
SSRAM Output Data Clock
SSRAM Clock for Inputs
SSRAM DLL Enable
ADM-XR-IIPro User Manual
User Manual
DDR2
SSRAM
DDR2
SSRAM
Version 0.2