Block Diagram - Yamaha 01v 96 Service Manual

Q P O N
BLOCK DIAGRAM 002 (01V96)
LCD Module
CN2(23P)
LCD MAIN
Contrast
CN1 CN006
(24P) (24P)
Bias
circuit
DC/DC
Backlight
converter
circuit
(5V 25V)
PN2
CN301(14P)
CN701(30P),
CN702(26P),
CN105(14P)
PN1 CN703(16P)
CN101(30P),
CN102(26P),
CN103(16P)
FD
CN001(34P) CN704(34P)
17
/
17 16
/ /
ATDIR Reset
28CA1-8826666-2
M L K J
IC019(80P)
LCD controller
W/40Kbyte SRAM
(S1D13704F)
LCD Reset
+5V
X30
Crystal
oscillator
60MHz
1/4
DPS block
(See Page 4)
DSP7 x 4
DSP6 x 2
SDRAM 16M x 4
DRAM 4M x 4
System Reset
System Reset
DSP Reset
System Reset
X131 X132
Crystal Crystal
oscillator oscillator
49.152MHz 45.1584MHz
1/2 1/2
External
WC
Selector
5
Address
/ DFS
Decoder &
Register
System Reset
IC143(14P)
PLL
96K/88.2K
TLC2932
IC001(208P)
Flash ROM SDRAM SRAM
Backup
32Mbit 64Mbit 4Mbit x 2
controller
LCD Reset
(16bit) (32bit) (32bit)
IC012(8P)
DSP Reset SH-3 CPU
IC007(48P) IC006(96P) IC008(44P),
(SH7709S) IC009(44P)
2Tr Reset
SCI0
DIR Reset
CPU: 132MHz
SCI2
BUS: 44MHz
ADA Reset Internal I/O: 22MHz
USB Reset
System Reset
System
Reset
Crystal
11MHz
RESET
X001
IC010(5P)
IC011(5P)
I H G
2ch/line
SM OUT
2ch/line
CR OUT
2ch/line
2
OMNI OUT 1-4 /
2ch/line
8
AIN 1-16
/
2ch/line
2Tr DIN
2ch/line
2Tr DOUT
4ch/line
2
SLOT2 IN
/
SLOT2 OUT /
2
4ch/line
4ch/line
4
SLOT1 IN /
SLOT1 OUT /
4
4ch/line
IC136(208P)
PLLP2
Master clock
Selector
1/2 44.1K x256
WC OUT
1/2 48K x256
SL clock
88.2K x256
96K x256
SLOT2 clock
WC x256
SLOT1 clock
2TR(256fs)
5
PLL
/
48K/44.1K
DIR2
IC144(44P)
DIR Reset
BT001
SCI0, SCI2
(2or4ch)
4
ATSC2A
/
IC401(144P)
/
4
(2or4ch)
System Reset
(System, Digital I/O, DSP, Panel Display, Operation Control)
F E D C
ADA
CN501(17P),
CN502(15P),
CN503(38P)
Analog I/O
(See Page 5)
STEREO L/R
MONI L/R
OMNI 1-4
SDATA 1-16
DFS
Master clock (MCLK, 64Fs, Fs)
ADA Reset
CN002(38P),
CN951(15P),
CN952(17P)
Digital I/O
2TR RMCK1
IC007
2ch/line DIR 2TR IN DIGITAL
CS8420
(COAXIAL)
IC501(28P)
JK002
IC011
2TR OUT
2ch/line
DIT
DIGITAL
CS8405
(COAXIAL)
IC504(28P)
2Tr Reset
WORD
CLOCK
IC009 JK005
IN
IC010 JK006
OUT
MIDI
JK001
IC004
SCI2(RX)
IN
IC005
SCI2(TX)
OUT
ATDIR Reset IC005
THRU
X451
PLL
Crystal
WC ATI
IC456
21MHz
(44P)
adat
OPTICAL
ATSC2A IN JK003
IC457(144P)
OUT JK004
System Reset
CPU
M37641 CN001
IC002 TO HOST
(80P) USB
USB Reset
MY SLOT
I/F
SCI0(RX)
SCI0(TX)
WC SLOT1
(2or4ch)
4
Selector /
Selector /
4
(2or4ch)
Hard: Digital Block
BLOCK DIAGRAM 002 (01V96)
B A
01V96
1
2
3
4
5
6
7
8
9
10
11
3 12