Honeywell bendis king KLN 94 Maintenance Manual page 35

BENDIX/KING
Three 8 bit latches are connected to the microprocessor data bus. An independent
DISCRETE_CSn signal for each latch is controlled by the WRn signal. If WRn is low and the ap-
propriate DISCRETE_CSn signal is low, the data from the DATA_BUS will be latched to the ap-
propriate output pin.
4.3.4.2.12.6.2
Bank selects signals (BS[5..0]) are latched and used with the the Six-Bit Adder. The Bank Select/
Six Bit Adder handles the appropriate decoding for the NAV Database extended block read fea-
ture. This feature is enabled when the DBXOVER_CSn signal is asserted low.
4.3.4.2.13 Dual Port Sram
The Dual Port Sram (U5008) is a 2kByte dual addressable static ram device for inter-microproces-
sor communications. The Host microprocessor and the Graphics microprocessor communicate
through this device. This allows information, such as display data, to be passed between the Host
and the Graphics microprocessors. Also, database information may be passed from the Compact
Flash Card, through the Graphics microprocessor, to the Host microprocessor.
4.3.4.2.14 Voltage Monitor Circuit
U5020 is an analog multiplexer. Various voltages are scaled and level shifted before entering
U5020. These levels can be monitored on a TEST page of the KLN 94. The internal ADC of the
Host microprocessor samples the PWRBUS signal which is an output of U5020. PBUS #0, PBUS
#1, and PBUS #2, are outputs of U5004 which accomplishes channel selection.
4.3.4.2.15 +5v Precision Reference/Temperature Transducer
A +5VDC reference (5VREF) is provided by U5019 to U5031 pin 72 for the Host microprocessor's
analog-to-digital (ADC) module. This signal is also used as a reference level for the front panel
backlight intensity level, the OBS sine and cosine filters, and for all annunciator detect compara-
tors. A V_TRIP comparator (U5037) uses 5VREF to provide a current sense trip voltage of -.085
VDC to the annunciator drivers for external short circuit detection. The reference IC (U5019) pro-
vides the unit temperature at pin 3. The voltage at this pin (approximately 2.1mV/K) is scaled by
U5011 before being applied to the Host microprocessor ADC where it is read as actual tempera-
ture.
4.3.4.2.16 OBS Circuits
4.3.4.2.16.1
The 450Hz signal required to excite the resolver is generated by DUART U5042. The square
wave is converted to a sine wave by a fourth order lowpass filter comprised of U5021-A, U5021-
B, and related components. The signal is then level shifted and amplified by the output driver
stage consisting of U5021-C, Q5020, Q5035, and related components.
U5021-D and related components form an over-current detector for the output circuit by compar-
ing the collector voltage of Q5020 with the driving signal. OBS OVERLOADn will be active when
output current is more than 70mA.
4.3.4.2.16.2
The sine and cosine outputs of the OBS resolver are read back via OBS SIN and OBS COS. Both
input circuits function identically so only operation of the OBS SIN will be described. The input
signal is level shifted and scaled to within +5V by R5062, R5040, R5182, C5069, CR5011 and
U5022-C. It is then filtered by a second order low pass filter consisting of R5183, R5049, C5055,
C5056 and U5022-A.
Page 4-36
Bank Select Generation.
OBS Output
OBS Inputs
15599M00.JA
KLN 94
Rev 0, Sept/2000