Honeywell bendis king KLN 94 Maintenance Manual page 32

BENDIX/KING
4.3.4.2.12.2.2
This avoids PERIPH bus contention with a possible previous PERIPH read operation.
4.3.4.2.12.2.3
These customized PERIPH_RDn and PERIPH_WRn signals are generated because the Com-
pactFlash card requires address and chip select hold times of 20ns following RDn or WRn deac-
tivation. Also, the read data from the CompactFlash card must be latched since the 386EX will
not read the data until the end of the cycle.
4.3.4.2.12.2.4
The EPLD state machine generates and outputs GRAPHICS_READYn to the 386EX in order to
control the length of a PERIPH or CF bus cycle. Besides controlling the length of the bus cycle,
the state machine also provides the control signals for the generation of GRAPHICS_BUF_ENn,
PERIPH_CF_Buf_ENn, PERIPH_RDn, PERIPH_WRn, and LATCH_EN.
4.3.4.2.12.2.5
This function generates the high and low byte chips selects for SRAM and CF from the
GRAPHICS_BHEn, GRAPHICS_BLEn, GRAPHICS_SRAM1_CSn, GRAPHICS_SRAM2_CSn,
and GRAPHICS_CF_CSn signals from the 386EX.
Inversions of the DPRAM interrupt signal to the 386EX.
The DPRAM interrupt output is active low. The EPLD simply inverts this signal since the 386EX
requires positive edge triggered interrupts.
4.3.4.2.12.2.6
The JTAG mode for the '386 microprocessor has bus cycles far slower than normal operation, so
the state machine must be disabled to prevent time-outs. In JTAG mode, the state machine nor-
mally controlling critical bus timing is disabled. Instead, PERIPH_WRn and
PERIPH_CF_BUF_ENn will follow GRAPHICS_WRn. GRAPHICS_BUF_ENn and PERIPH_RDn
will follow GRAPHICS_RDn. A JTAG programming/debugging program hosted on a notebook PC
must cause GRAPHICS_CF_CSn, GRAPHICS_CODE_CSn, and GRAPHICS_SRAM1_CSn to
all go low all at the same to enter JTAG mode. Exiting JTAG mode is done by either bringing
MAIN_RESETn low, or by bringing GRAPHICS_CODE_CSn, GRAPHICS_SRAM1_CSn, and
GRAPHICS_DPRAM_CSn low at the same time.
4.3.4.2.12.2.7
It was found that the Sandisk Compact Flash cards do not utilize the variable bus timing of the
common memory mode. SanDisk only uses fixed bus timing similar to the attribute mode. In par-
ticular, the CF card does not implement WAITn signaling. Fixed wait states must be used. There-
fore, REGn has been internally tied low in the EPLD logic to cause the state machine to use fixed
bus timing similar to the attribute mode during CF accesses.
Rev 0, Sept/2000
Generation of control signals for buffering and multiplexing of the 386EX
data bus, PERIPH_BUS, and CF_BUS.
Generation of customized RDn and WRn signals for PERIPH_BUS and
CF_BUS accesses.
Wait state and GRAPHICS_READYn generation for PERIPH_BUS and
CF_BUS accesses.
Generation of high and low byte chip selects for 386EX SRAM and CF ac-
cess.
JTAG Mode timing adjustment.
REGn Modification.
15599M00.JA
KLN 94
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