Graphics Microprocessor Interrupts; Graphics Microprocessor Discrete I/O - Honeywell bendis king KLN 94 Maintenance Manual

BENDIX/KING
PIN LABEL
NMI G_WDTOUT
INT0 CF_READY
INT1 CF_PRESENT
INT2 GRAPHICS_INT
INT3 Not Used
The Graphics microprocessor has port addressable I/O pins that can be used to monitor discrete
lines going to the microprocessor and also control discrete lines going from the microprocessor.
These lines are shown in the following table along with their description.
LABEL PIN
VIDEO_RESET P1.0_DCD0*
CF_REGn P1.1_RTS0*
CF_RESET P1.2_DTR0*
VPP P1.3_DSR0*
TMCP_ENABLEn P1.7_HLDA
4.3.4.2.8 VPP and Compact Flash VCC
Normal operation for the Flash memory devices occurs when the VPP signal of U5003 pin 13 is
GND. This output is controlled by GRAPHICS_RESET and HW_PGM_EN signals. When both
the GRAPHICS_RESET signal and HW_PGM_EN are low, then VPP is grounded and normal
read accesses are done on the Flash memory devices. When HW_PGM_EN is high and
GRAPHICS_RESET is low, then the FLASH memory devices can be written to and programmed.
The Compact Flash VCC (CF_VCC) signal line on pins 16, 14 and 2 supplies the 5 volt power to
the Compact Flash Card and protects the line from over-current transients which may occur if the
card is removed or replaced while the unit is on.
4.3.4.2.9 Graphics Flash Memories
The 8Mbit (512k x 16) flash memory (U5017) has a 16kbyte boot block. The boot block is a spe-
cial address memory location within the flash device. It has specific addressing/encoding require-
ments which ensure that the boot block is locked for all normal programming and read operations.
For read operations, GRAPHICS_CODE_CSn is low, PERIPH_RDn is low, and PERIPH_WRn is
held high due to the decoding logic of U5038.
Rev 0, Sept/2000
TABLE 4-6 Graphics Microprocessor Interrupts
I/O DESCRIPTION
O 1 = video controller chip is placed in reset
0 = normal operation
O 1 = Compact Flash common memory plane is enabled
0 = Compact Flash attribute memory plane is enabled
O 1 = Compact Flash card is placed in reset
0 = normal operation
I 1 = Vpp has been enabled by the hardware, so code Flash memory
may be programmed
0 = normal operation
I 1 = normal operation
0 = TMCP interface is active
TABLE 4-7 Graphics Microprocessor Discrete I/O
15599M00.JA
DESCRIPTION
Goes high when internal watchdog times out.
Goes high when the Compact Flash card is ready for
the next data transfer.
Goes high when the Compact Flash card is inserted
into the socket.
Goes high when the dual port RAM asserts an inter-
rupt
KLN 94
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