Figure 20. 2 × 2 Binning - Princeton PIXIS-XB System User Manual

Chapter 5
Hardware Binning
Hardware binning is
performed on the CCD array
before the signal is read out of
the output amplifier. For
signal levels that are readout
noise limited this method
improves S/N ratio linearly
with the number of pixels
grouped together. For signals
large enough to render the
camera photon shot noise
limited, the S/N ratio
improvement is roughly
proportional to the square-
root of the number of pixels
binned.
Binning also reduces readout
time and the burden on
computer memory, but at the
expense of resolution. Since
shift register pixels typically
hold only twice as much
charge as image pixels, the
binning of large sections may
result in saturation and "blooming," or spilling of charge back into the image area.
Figure 20 shows an example of 2  2 binning. Each pixel of the image displayed by the
software represents 4 pixels of the CCD array. Rectangular bins of any size are possible.
Binning also reduces readout time and the burden on computer memory, but at the
expense of resolution. Since shift register pixels typically hold only twice as much charge
as image pixels, the binning of large sections may result in saturation and "blooming," or
spilling of charge back into the image area.
The readout rate for n  n binning is approximated using a more general version of the
full resolution equation. The modified equation is:
Software Binning
One limitation of hardware binning is that the shift register pixels and the output node are
typically only 2-3 times the size of imaging pixels. Consequently, if the total charge binned
together exceeds the capacity of the shift register or output node, the data will be corrupted.
Operation


t t



sr v
t  N N
   
R
 x y
2
 
n n



Figure 20. 2 × 2 Binning





 
 N t
 
 
 
x i

 



41
41
(3)