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EV80C196KB Microcontroller Evaluation Board User's Manual 4 3-
The BUSWIDTH output of the EPLD, pin 16, is fed into the buswidth pin of the
8OC196KB. Therefore, it is driven low for accesses to 8-bit memory and high for
accesses to 16-bit memory. As shipped, it goes low simultaneously with CE2 or
CS510 as these are the only areas of memory mapped as 8-bit.
Programmed into the EPLD is a 3-bit wait-state machine clocked by the rising edge
of CLKOUT from the 8OC196KB. The transition sequence of the wait-state machine
is controlled by the current state of the machine and the inputs to the EPLD (for
further details see appendix E). While the bus of the 80C196KB is idle the wait-state
machine is locked in state 0, which is called async-start. The conditions for leaving
async-start are 1) ALE being asserted, 2) HLDA# not being asserted and 3) a
value on A8 - Al5 requiring wait-states. Because the falling edge of ALE can occur
before the next rising edge of CLKOUT can clock the wait-state machine, a signal
called STALE (for Stretched ALE) is used. STALE does not go low until after the
rising edge of CLKOUT.
During async-start, the output WAIT# from the EPLD is asserted asynchronously
based upon a value on A8-A15 requiring wait-states. If no wait-states are required,
WAIT# will not be asserted and the wait-state machine will remain in async-start.
However, if one or more wait-states are needed WAIT# will be asserted and the
wait-state machine will transition out of async-start on the next rising edge of
CLKOUT. The next state entered depends on how many wait-states are needed. If
only one is required the next state is remove&old, where WAIT# is deasserted
regardless of the inputs to the EPLD. If two watt-states are needed the next state is
hold-2, where WAIT# is always asserted, then the state after that is remove-hold.
The additional states,
hold-3
- hold 7, work just like hold-2 with WAIT# always
asserted. The wait-state machine wJI count through from hold-2 to hold-n to
generate n wait-states before jumping to remove-hold to deassert WAIT#. The
maximum number of wait-states is seven.
The previous paragraph described how the signal WAIT# is generated based on the
rising edge of CLKOUT. However, the 8OC196KB needs to have a valid signal on
it's READY input pin until the falling edge of CLKOUT. Therefore, it was necessary
to clock WAIT# through a negative-edge-triggered-JK flip-flop (U15A) by the falling
edge of CLKOUT to generate a signal called WAITN#. As in the EPLD, WAITN# is
asserted asynchronously while ALE is high and WAIT# is asserted. After ALE goes
low WAITN# will remain asserted until WAIT# is deassetted and the flip-flop is
clocked. Besides the WAIT# signal, the WAITN# signal can be asserted by the
USEREADY signal from the expansion bus. As shipped, the EPLD has the following
configuration:
Memory
Wait
Type
States
ROMsim/RAM
0
ROMsim/RAM
0
Monitor EPROM
1
82510 UART
2
Unimplemented
0
Unimplemented
1
Enable
Signal
CEl
CE2
CEO
cs510
N/A
N/A
Memory Region
in User Mode
2000H-5FFFH
6000H-7FFFH
0-FFH, 1 DOOH- DFFH
1 EOOH-1 EFFH
1 OOH-1 CFFH, COOOH-FFFFH
8000H - BFFFH
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