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Trldv = 60 ns MAX, for zero wait states.
Trldv(ROMsim)
= 50 ns (RAM Toe MAX).
Trldv = 226 ns MAX, for one wait state.
Trldv(EPROM)
= 75 ns (EPROM Toe MAX).
Trldv = 393 ns MAX, for two wait states.
Trldv(UART)
= 281 ns (UART Trldv MAX).
Tcldv is 'irrelevant in this design.
Trhdz = 63 ns MAX.
Trhdz(ROMsim)
= 35 ns (RAM Tohz MAX).
Trhdz(EPROM)
= 55 ns (EPROM Tdf MAX).
Trhdz(UART)
= 40 ns (UART Trhdz MAX).
Trxdx = 0 ns MIN.
Trxdx(ROMsim)
= 0 ns (RAM Tohz MIN).
Trxdx(EPROM)
= 0 ns (EPROM Toh MIN).
Trxdx(UART)
is not specified.
Txhch is irrelevant in this design.
Tclcl = 166 ns.
Tclcl(WAIT) = 55 ns (PAUEPLD
Tp MIN).
= 10 ns (AC1 12 l/Fmax
MIN).
Tchcl = 73 ns MIN.
Tchcl(WAIT)
= 25 ns (PAUEPLD
Tco MAX) + 35 ns (PAUEPLD Tpd MAX)
+ 4 ns (AC1 12 Tsu MIN)
= 64 ns.
or = 25 ns (PAUEPLD
Tco MAX) + 35 ns (PAUEPLD
Tpd MAX)
+ 8 ns (AC08 Tplh MAX) + 2 ns (AC1 12 Trem MIN)
= 70 ns.
Tcllh is irrelevant in this design.
Tllch is irrelevant in this design.
Tlhlh is irrelevant in this design.
Tlhll = 73 ns MIN.
Tlhll(AO-A15) = 5 ns (AC373 Tw MIN).
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