SOLTEK SL-65LIV User Manual page 60

65LIV
CPU to PCI Write
Buffer
PCI Dynamic Burst-
PCI Master 0 WS
PCI Delay Transac-
PCI # 2 Access # 1
AGP Master 1 WS
AGP Master 1 WS
Memory Parity/ECC
Check
3. Press <ESC> to return to the Main Menu when you finish setting up all
items.
When this field is Enabled, writes from the CPU to
the PCI bus are buffered, to compensate for the
speed defferences between the CPU and the PCI
bus. When Disabled, the writes are not buffered and
the CPU must wait until the write is complete before
starting another write cycle.
The choices: Enabled; Disabled.
When Enabled, every write transaction goes to the
ing write buffer. Bursting transactions then burst on the
PCI bus and non-bursting transactions don't.
The choices: Enabled; Disabled.
When Enabled, writes to the PCI bus are executed
Write with zero wait states.
The choice: Enabled, Disabled.
Leave this field at default
tion The choice: Enabled, Disabled.
Leave this field at default
The choice: Enabled, Disabled(default).
Retry
Leave this field at default
Write The choice: Enabled, Disabled(default).
Leave this field at default
Read The choice: Enabled, Disabled(default).
This item enabled to detect the memory parity and
Error Checking & Correcting.
The choices: Enabled; Disabled.
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