SOLTEK SL-65LIV User Manual page 58

65LIV
2. Use one of the arrow keys to move between options and modify the
selected options by using PgUp / PgDn / + / - keys. An explanation of the
<F> keys follows:
<F1>: "Help" gives options available for each item.
<F5>: Get the previous values. These values are the values with which the
user starts the current session.
<F6>: Load all options with the BIOS default values.
<F7>: Load all options with the Setup default values.
DRAM Clock This item allows you to control the DRAM speed.
DRAM Timing by SPD When this item is Enabled, DRAM Timing is set by
SDRAM Cycle Length Select CAS latency time in HCLKs of 2 or 3. The
Bank Interleave Please use default setting.
Memory Hole In order to improve performance, certain space in
P2C/C2P
Concurrency
Fast R-W Turn
Around
The choices: Host Clock; HCLK+33M; HCLK-33M.
SPD. SPD (Serial Presence Detect) is located on
the memory modules, BIOS reads information coded
in SPD during system boot up.
system designer already set the values. Do not
change the default value unless you change speci-
fications of the installed DRAM or the installed CPU.
The choices: Disabled; 2 Bank; 4 Bank.
memory is reserved for ISA cards. This memory must
be mapped into the memory space below 16MB.
The choices: 15M-16M; Disabled.
This item allows you to enable/disable the PCI to
CPU, CPU to PCI concurrency.
The choices: Enabled; Disabled.
This item controls the DRAM timing. It allows you to
enable / disable the fast read / write turn around.
The choices: Enabled; Disabled.
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