System Timers; Operation - Mitsubishi Electric LS Pro Hardware Technical Reference

System timers

The SCAMP chip provides a three channel 82C54 compatible system timer.
The counters are:
counter 0
counter 1
counter 2
Full details on the operation of 8254 counters are given in the manufacturers
data sheets and are not repeated here.
The system timers are programmed by accessing the four I/O ports recognised
by the timers. The counters provide six modes of operation. The four I/O ports
which are used to program the counters are organised as one count register
for each counter and one control byte (I/O ports 0040h to 0043h). The function
of each port is given in section 5.

Operation

The clock input to the timer is 1.193 MHz. This is obtained by dividing the14.31818 MHz
system oscillator (OSC) by twelve. The output frequency of each timer is then
separately programmed by loading the associated count register.
System timer
BIOS loads the counter 0 registers with a value of 65536 which results in a
system timer frequency of approximately 18.2Hz. The output of counter 0
generates a hardware interrupt, IRQ0, which is used to maintain a time of day
clock based on the number of "ticks" since midnight.
Refresh request
The BIOS loads the counter 1 registers with a value of 18 which generates a
refresh request rate of 66.278kHz (one refresh request every 15.08 µseconds).
A refresh request puts the processor into hold and accesses memory via a DMA
type operation.
Sound output
The sound output may be set to give the output frequency required. To enable
the output bit 0 of Port B (I/O 0061h) must be set to 1.
system timer
refresh request
sound output
LS PRO HARDWARE TECHNICAL REFERENCE 3/9
System Board