Dma I/O Address Map - Mitsubishi Electric LS Pro Hardware Technical Reference

DMA I/O address map

The following table shows the I/O addresses used by the DMA Controller and their
significance. Full information on the programming of 8237 DMA controller registers are
given in manufacturers data sheets and are not repeated here
Address (hex)
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
000A
000B
000C
000D
000E
000F
0080
0081
0082
0083
0087
0089
008A
008B
008F
00C0
00C2
00C4
00C6
00C8
00CA
00CC
00CE
00D0
00D4
00D6
00D8
00DA
00DC
00DE
Memory and I/O Usage
Function
Channel 0 Memory address register
Channel 0 Transfer count register
Channel 1 Memory address register
Channel 1 Transfer count register
Channel 2 Memory address register
Channel 2 Transfer count register
Channel 3 Memory address register
Channel 3 Transfer count register
Channel 0-3 Status register
Reserved
Channel 0-3 Mask Register (set/reset)
Channel 0-3 Mode register (write)
Clear byte pointer (write)
Master clear (write)
Channel 0-3 Clear mask register (write)
Channel 0-3 Write mask register
Diagnostic checkpoint port
Channel 2 Page table address register
Channel 3 Page table address register
Channel 1 Page table address register
Channel 0 Page table address register
Channel 6 Page table address register
Channel 7 Page table address register
Channel 5 Page table address register
Channel 4 Page table address register
Channel 4 Memory address register
Channel 4 Transfer count register
Channel 5 Memory address register
Channel 5 Transfer count register
Channel 6 Memory address register
Channel 6 Transfer count register
Channel 7 Memory address register
Channel 7 Transfer count register
Channel 4-7 Status register
Channel 4-7 Mask register (set/reset)
Channel 4-7 Mode register (write)
Clear byte pointer (write)
Master clear (write)
Channel 4-7 Clear mask register (write)
Channel 4-7 Write mask register
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