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System Board
The Ethernet port occupies a group of 17 I/O ports. The ports have the following
significance:
Location (Hex)
82596 LAN
The 82596 is connected to the processor local bus. The 82596 is an intelligent co-
coprocessor
processor which performs many network control tasks.
The inherent intelligence of the 82596 reduces host processor overhead, and allows
all time critical functions to be performed independently of the host. This along with
the inherent speed of the processor local bus results in a high performance network
interface, with minimum host processor overhead.
The host processor monitors and controls the 82596 through a shared memory
structure known as the System Control Block (SCB). The 82596 uses the HOLD and
HOLDA signals to gain control of the local bus in order to access the SCB.
Both the 82596 and the host can modify the SCB. The processor uses the Channel
Attention (CA) line to notify a change to the 82596, while the 82596 generates a
hardware interrupt if it has modified the SCB.
The host can communicate with the 82596 via a single port (PORT). This allows the
host to, amongst other things, reset the 82596.
Full details on the 82596 and its operation are given in the manufacturers data sheets.
82C503 dual
The 82503 dual serial transceiver (DST) incorporates all the active circuitry necessary
serial transceiver
to interface the 82596 to an AUI port and a TPE network. In addition to the normal
features of an IEEE 802.3 transceiver the 82503 also incorporates automatic port
selection, and polarity switching.
Automatic port selection selects either TPE or the AUI port without external
intervention. If a good TPE connection is available the 82503 will select the TPE port,
if no TPE connection is available the AUI port will be selected.
Note
The thin cable Ethernet port is derived from the AUI port. To select thick or thin Ethernet, SW1
must be in the correct position.
Automatic polarity selection allows the 82503 to overcome the most common wiring
problem on TPE networks. If the polarity of the receive signal pair is reversed as a result
of a crossed pair of wires, the 82503 automatically corrects the error by reversing the
signals internally.
7997
The Ethernet transceiver chip acts as the interface between thick and thin Ethernet
cabling standards, implementing the IEEE802.3 10BASE2 standard.
3/20 LS PRO HARDWARE TECHNICAL REFERENCE
Significance
0
Port
1-3
Reserved
4
CA
5-7
Reserved
8-D
Ethernet Address
E
Reserved
F
Checksum
10
Status register
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