Pioneer AVIC-Z2/XU/UC Service Manual page 303

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1.4.5 Back-end video circuit section (only for the video-type models)
A
The composite video signal from the video DAC circuit inside the AVLSI is output from the HOST I/F via the video
buffer circuit.
IC1503
AVLSI
Video
B
DAC section
1.4.6 Back-end SDRAM I/F section (only for the video-type models)
For the SDRAM, which functions as the communication I/F between the AVLSI and the memory, a 64Mbit IC has
employed to secure the MPEG stream dada buffer.
C
D
1.4.7 Back-end microcomputer I/F section (only for the video-type models)
This section works as a communication interface between the AVLSI and the CPU.
In order to match the operating frequency for the CPU with that for the AVLSI, a frequency dividing circuit is inserted
as shown below.
E
F
14
1
2
Q1501 peripheral
Video buffer circuit
COMP
IC
1501
SDRAM
IC1701 A1-A17
CPU
DO-D15
XCSAVR
XCSAVW
XAVINT
XRD
CLKOUT
XSRAMWR
Microcomputer interface
2
3
AVCC5
Video circuit
IC1503
MA0-11
AVLSI
MDQ0-15
MCK
XWE
XCAS
XRAS
XCSM(XCSE)
DQMUM(DQMUE)
DQMLM
SDRAM interface
IC1706
XCSAV
IC1502
HCLK
IC1504
IC1505
XHWR
Dividing
circuit
C X - 3 01 6
3
4
CN1611
HOST I/F
COMPO
IC1503
AVLSI
4