Gpio_Ctrl_Pin: 1110H-1140H - Point Grey Flea3 GigE Technical Reference

Point Grey Flea3 GigE Technical Reference
E.4

GPIO_CTRL_PIN: 1110h-1140h

These registers provide control over the GPIO pins.
Pin Register
0 GPIO_CTRL_PIN_0
1 GPIO_CTRL_PIN_1
2 GPIO_CTRL_PIN_2
3 GPIO_CTRL_PIN_3
Format:
Field
Presence_Inq
Pin_Mode
Data
Pwm_Count
En_Pin
Disable_Pol
En_En
Pwm_Pol
Revised 10/29/2013
Copyright ©2010-2013 Point Grey Research Inc.
1110h
1120h
1130h
1140h
Bit
Presence of this feature
[0]
0: Not Available, 1: Available
[1-11] Reserved
Current GPIO Mode:
0: Input
1: Output
[12-15]
2: Asynchronous Trigger
3: Strobe
4: Pulse width modulation (PWM)
For Modes 0, 1, and 2: Reserved
[16-30]
For Mode 4 (PWM:) see below
For Modes 0, 1, and 2: Data field
0 = 0 V (falling edge), 1 = +3.3 V (rising edge)
[31]
For Mode 4 (PWM): see below
Number of PWM pulses
Read: The current count; counts down the remaining pulses. After reaching zero, the count does
[16-23] not automatically reset to the previously-written value.
Write: Writing the number of pulses starts the PWM. Write 0xFF for infinite pulses. (Requires
write of 0x00 before writing a different value.)
[24] Reserved
The GPIO pin to be used as a PWM enable i.e. the PWM continues as long as the En_Pin is held
[25-27]
in a certain state (high or low).
[28] Reserved
Polarity of the PWM enable pin (En_Pin) that will disable the PWM. If this bit is 0, the PWM is
[29]
disabled when the PWM enable pin goes low.
0: Disable enable pin (En_Pin) functionality
[30]
1: Enable En_Pin functionality
Polarity of the PWM signal
[31]
0: Low, 1: High
E Control and Status Registers
Description
113