NEC MultiSync LCD1920NX User And Service Manual page 118

Reserved Pin Description
Pin Name
Reserved
Power and Ground Pin Description
Pin Name
VCC
GND
OVCC
OGND
AVCC
AGND
PVCC
PGND
Configuration Pins Description
Pin Name
OCK_INV
PIXS
DFO
STAG_OUT
ST
Pin # Type
99 In
Pin # Type
6,38,67 Power
5,39,68 Ground
18,29,43,57,78 Power
19,28,45,58,76 Ground
82,84,88,95 Power
79,83,87,89,92 Ground
97 Power
98 Ground
Pin # Type
100 In
4 In
1 In
7 In
3 In
Description
Must be tied HIGH for normal operation.
Description
Digital Core VCC, must be set to 3.3V.
Digital Core GND.
Output VCC, must be set to 3.3V.
Output GND.
Analog VCC must be set to 3.3V.
Analog GND.
PLL Analog VCC must be set to 3.3V.
PLL Analog GND.
Description
ODCK Polarity.
A LOW level selects normal ODCK output. A HIGH
level selects inverted ODCK output. All other output
signals are not affected by this pin. They will
maintain the same timing no matter the setting of
OCK_INV pin.
Pixel Select.
A LOW level indicates one pixel (up to 24-bits) per
clock mode using
QE[23:0] A HIGH level indicates two pixels (up to
48-bits) per clock mode using
QE[23:0] for first pixel and QO[23:0] for second
pixel.
Output Data Format.
For all DVI applications, this pin should be tied
LOW.
Staggered Output.
A HIGH level selects normal simultaneous outputs
on all odd and even data lines. A LOW level selects
staggered output drive. This function is only
available in 2-pixels per clock mode.
Output Drive.
A HIGH level selects HIGH output drive strength. A
LOW level selects LOW output drive strength.
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