2.11.4 Pin description
Pin Name
SCDT
PDO
PD
Differential Signal Data Pin Description
Pin Name
RX0+
RX0-
RX1+
RX1-
RX2+
RX2-
RXC+
RXC-
PDO
Pin #
Type
8
Out
9
In
2
In
Pin #
Type
90
Analog
91
Analog
85
Analog
86
Analog
80
Analog
81
Analog
93
Analog
94
Analog
9
In
Description
Sync Detect.
A HIGH level is outputted when DE is actively
toggling indicating that the link is alive. A LOW level
is outputted when DE is inactive, indicating the link
is down. Can be connected to PDO to power down
the outputs when DE is not detected. The SCDT
output itself, however, Remains in the active mode
at all times.
Output Driver Power Down (active LOW).
A HIGH level indicates normal operation. A LOW
level puts all the output drivers only (except SCDT
and CTL1) into a high impedance (tri-stats) mode. A
weak internal pull-down device brings each output
to ground. PDO is a sub-set of the PD description.
The chip is not in power-down mode with this pin.
There is an internal pull-up resistor that defaults the
chip to normal operation if left unconnected. SCDT
and CTL1 are not tri-stated by this pin.
Power Down (active LOW).
A HIGH level indicates normal operation and a
LOW level indicates power down mode. During
power down mode, all output buffers are disabled
and brought low, all analog logic is powered down,
and all inputs are disabled.
Description
TMDS Low Voltage differential Signal input data
pairs.
TMDS Low Voltage differential Signal input data
pairs.
Impedance Matching Control.
Resistor
value
should
characteristic impedance of the cable. In the
common case of 50Ω transmission line, an external
500Ω resistor must be connected between AVCC
and this pin.
7-25
be
ten
times
the
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