H/V-Sync Processing - NEC MultiSync LCD1920NX User And Service Manual

2.6.4 H/V-sync processing

H/V Polarity Detection
The Polarity functions detect the input HSYNC/VSYNC high and low pulse duty pluse. If the high pluse
duration is longer than that of the low pluse, the negative polarity is asserted; otherwise, positive polarity is
asserted. The HPLchg interrupt is set when the Hpol value changes. The VPLchg interrupt is set when the
Vpol value changes.
Output HBLANK/VBLANK Control and Polarity Adjustment
The HBLANK is the mux output of HSYNC and self-test horizontal pattern. The VBLANK is the mux output
of VSYNC, CVSYNC and the self-test vertical pattern. The mux selection and output polarity are S/W
controllable. The VBLANK output is cut off when VSYNC frequency is over 200Hz or 133Hz depends on
8MHz/12MHz OSC selection. The HBLANK/VBLANK shares the output pin with P4.1/P4.0
VSYNC interrupt
MTV112MN32 checks the VSYNC input pluse and generates an interrupt at its leading edge. The
VSYNC1 flag is set each time MTV112MN32 detects a VSYNC pluse.
H/V SYNC Processor Block Diagram
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