Ddc & Iic Interface - NEC MultiSync LCD1920NX User And Service Manual

2.6.5 DDC & IIC Interface
DDC1 Mode
MTV112MN32 enters DDC1 mode after Reset. In this mode, VSYNC is a data clock. The HSCL pin should
remain at high. The data output to the HSDA pin is taken from 8 bytes FIFO in MTV112MN32.
MTV112MN32 fetches the data byte from FIFO, then sends it in a 9-bit packet format which includes a null
bit (=1) as packet separator. The software program should load EDID data (original stored in EEPROM)
into FIFO and take care of the FIFO depth. FIFO sets the FIFOI (FIFO low interrupt) flag when there are
fewer than N (N=2,3,4 or 5 controlled by LS1, LS0) bytes to be output to the HSDA pin. To prevent FIFO
from emptying, software needs to write EDID data to FIFO as soon as FIFOI is set. On the other hand,
FIFO sets the FIFOI flag when its capacity is full. Software should not write additional data to FIFO in such
instance. The FIFOI interrupt can be masked or enabled by an EFIFO control bit. A simple way to control
FIFO is to set (LS1, LS0=1,0) and enable FIFOI interrupt, then software may load 4 bytes into FIFO each
time a FIFOI interrupt arises. A special control bit "LDFIFO" can reduce the software effort when EDID data
is stored in EEPROM. If LDFIFO=1, FIFO will be automatically loaded with MBUF data when software
reads MBUF XFR.
DDC2B Mode
MTV112MN32 switches to DDC2B mode when it detects a high to low transition on the HSCL pin. Once
MTV112MN32 enters DDC2B mode, the host can access the EEPROM using IIC bus protocol as if the
HSDA and HSCL are directly bypassed to ISDA and ISCL pins. MTV112MN32 will return to DDC1 mode if
HSCL is kept high for a 128 VSYNC clock period. However, it will lock in DDC2B mode if a valid IIC access
has been detected on HSCL/HSDA bus. The DDC2 flag reflects the current DDC status. S/W may clear it
by setting CLRDDC. Control bits M128/M256 are used to block the EEPROM write operating from the host
if the address is over 128/256.
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