NEC MultiSync LCD1920NX User And Service Manual page 117

Output Pins Description
Pin Name
QE23 - QE0
QO23 - QO0
ODCK
DE
HSYNC
VSYNC
CTL1
CTL2
CTL3
Pin # Type
See SiL161A Out
Pin Diagram
See SiL161A Out
Pin Diagram
44 Out
46 Out
48 Out
47 Out
40 Out
41 Out
42 Out
Description
Output Even Data [23:0] corresponds to 24-bit pixel
data for 1-pixel/clock input mode and to the first
24-bit pixel data for 2-pixels/clock mode.
Output data is synchronized with output data clock
(ODCK).
Refer to the TFT Signal Mapping application note
(SiL/AN-0007) which tabulates the relationship
between the input data to the transmitter and output
data from the receiver.
A low level on PD or PDO will put the output drivers
into a high impedance (tri-state) mode. A weak
internal pull-down device brings each output to
ground.
Output Odd Data [23:0] corresponds to the second
24-bit pixel data for 2-pixels/clock mode.
During 1-pixel/clock mode, these outputs are driven
low.
Output data is synchronized with output data clock
(ODCK).
Refer to the TFT Signal Mapping application note
(SiL/AN-0007) which tabulates the relationship
between the input data to the transmitter and output
data from the receiver.
A low level on PD or PDO will put the output drivers
into a high impedance (tri-state) mode. A weak
internal pull-down device brings each output to
ground.
Output Data Clock.
This output can be inverted using the OCK_INV pin.
A low level on PD or PDO will put the output driver
into a high impedance (tri-state) mode. A weak
internal pull-down device brings the output to
ground.
Output Data Enable.
This signal qualifies the active data area. A HIGH
level signifies active display time and a LOW level
signifies blanking time. This output signal is
synchronized with the output data. A low level on
PD or PDO will put the output driver into a high
impedance (tri-state) mode. A weak internal
pull-down device brings the output to ground.
Horizontal Sync input control signal.
Vertical Sync input control signal.
General output control signal 1.
This output is not powered down by PDO.
General output control signal 2.
General output control signal 3.
A low level on PD or PDO will put the output drivers
(except CTL1 by PDO) into a high impedance
(tri-state) mode. A weak internal pull-down device
brings each output to ground.
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