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SECTION 4
-
THEORY OF OPERATION
4.1 INTRODUCTION
This section contains circuit descriptions
of the Model 706. The
information
is arranged to provide a description
of individual
functional
circuit blocks. To facilitate
understanding,
the de-
scriptions are referenced to Figure 4-1, which is an overall block
diagram of the Model 706. Detailed schematics
of the Model
706 are located in Section 6.
4.2 POWER SUPPLY
To aid in understanding
of the following
discussion, refer to
the
block diagram in Figure 4-1.
The power supply is a6V switching supply with 6Acurrent capa-
bility. The AC input may range from 95V to 125V or 210V to
250V depending
on internaliy selected jumpers. Refer to Sec-
tion 5 Maintenance
for complete details. The supply operates
on line frequency
from 47Hz to 44OHz. Regulation of the line
and load is &0.15% with noise and ripple being a maximum of
5mV p-p.
The supply has an inherent solid state short circuit protection.
An automatic
current limiting circuit limits the output current
whjch provides protection for the instrument as well as the sup-
ply. There is also a thermal circuit breaker to provide thermal
overload protection.
4.3 MICROCOMPUTER
To simplify understanding
of the following discussion
refer to
the block diagram
in Figure 4-1 and schematic
diagram
705-I 06 sheet 3 of 3.
The microcomputer
includes
a 6808 microprocessing
unit
(CPU) UlO5, a 6522 versatile interface adapter [VIA) U120, two
2764 ROMs, Ui 06 and U107. The microcomputer
also consists
of two 6116s RAMS U108 and U109, an address decoder
LSI 38 (Ui 16), an asynchronous
communication
interface
adapter
(ACIA) U103 and assorted
buffers and line
drivers
UYO4, U110, U118, U126, U122, Ul19, Ulll
and U112. The
threshold detection and reset circuit consists of Uf 15 and asso-
ciated components.
If the power supply voltage level drops be-
low 4.5V for some reason, U115 resets the Model 706. The bat-
tery backup circuitry and clock circuitry consist of U121, U 123,
U124, U127, Ql 01, QI 02, Y102 and associated components.
The IEEE-488 interface circuitry consists of a 9914 general pur-
pose interface bus adapter U102, Ul 01 and U113 are general
purpose bus transceivers.
The memory used in this system is
shown in the memory map Figure 4-2. Interfacing of the micro-
processor with the RAMS, ROMs, Front Panel, VIA, ACIA or
IEEE-488 interface circuitry is controlled
by the address de-
coder, Ul ? 6.
Partial address decoding is used
in
this system. The function
selected is determined by the state of the Al 3, Al 4 and Al 5 ad-
dress lines. These address lines determine which output is se-
lected by the decoder U116 in accordance
with the memory
map. Only one of these device (ROM, RAM, VIA, ACIA, etc.) will
have access to the data bus at any one time. The address de-
coder selects one of the devices only after a valid memory ad-
dress (VMA) has been asserted at the decoders input Gi (pin
6). The VMA signal is generated by the 6808 microprocessor.
Timing for the computing sequences is provided by 4MHz
crys-
tals Yl 01. The 6808 microprocessor
divides
this signal by four
to produce a 1 MHz signal at the E (pin 37) output. This is a sin-
gle phase TTL compatible clock. The clock may be conditioned
by a memory read signal. This output is capable of driving one
standard TTL load and 13OpF.
U115 and its associated circuitry form a reset circuit which re-
sets the microprocessor
VIA, ACIA and IEEE-488 interface cir-
cuitry. The circuit actuates in the event the front panel display is
not updated after a specific period of time (e.g. interval time) has
elapsed due to a lost program or power line transient. The circuit
also works as a threshold detector circuit.
As seen in schematic 705106 sheet 3 of 3. the data lines run-
ning throughout the microcomputer
circuitry are labeled as DO
through D7. The address lines running throughout the micro-
computer circuitry are labeled as A0 through Al 5.
The serial out and alarm/serial
in outputs are controlled by the
ACIA (U103). R109 and RI10 and CR103 comprise a protec-
tion network for these two outputs. The serial out output data is
transmitted, via RI 10 and pin 6 of the ACIA (Ui 03). The alarm/
serial
in data
is transmitted/received
via R109 and pin 2 of the
ACIA. The external trigger input and channel ready output are
controlled by the VIA, U120. RlO8, RI I$ and CR1 02 compn'se
a protection circuit for these two connectors, while RI 12 is a pull
up resistor for the external trigger line. The external trigger input
is
routed into the circuitry via
Rl 11 and pin 40 of the VIA, Ul20.
The channel ready output produces a TTL level negative going
pulse of greater than 1 Opsec by way of RI 08 and pin 15 of the
VIA when programmed
to do so.
The control of the relay switching is accomplished
by the paral-
lel
data
on the data bus being buffered by U110 and sent
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4-1
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