Displaycircuit; Ieee-488Lnterfacecircuitry - Keithley 706 Instruction Manual

MEMORY MEMORY
ADDRESS ADDRESS
IN HEX IN HEX
COMPONENT COMPONENT
am
"r-----l
I
2k*8 CMOS MEMORY I 6116
I
2k"8 CMOS MEMORY 4 5116
ACIA SERIAL
COMMUNICATION CHIP
BFFF
--w-s,
6oat
I
STROBE LINES FOR MATRIX
CARD SHIFT REGISTERS
VIA VERSATILE
I 5522
INTERFACE ADAPTER
I
IEEE INTERFACE
' 3914A
RELAY DRIVE AND DISPLAY
BOARD BUSS BUFFER I
STROBE LINES
8k*8 ROM 1764
DFFF I
I jSAE4l
8k*8 ROM
2764
FFFF L-m--m-
Figure 4-2. Model 706 Memory Map
Figure 4-2. Model 706 Memory Map
to octal latches U421 through U438. The address lines A0
through A3 are buffered by U118 and that output is decoded
by Ul 1 I, U112 and U119. This information is the clock input
for each octal latch. When the appropriate information arrives
(pulse), the corresponding octal latch releases its data to the
proper current drivers which in turn drive the relays on the
cards. Pins 25 through 33 on connector J/P1020 transmits
the buffered parallel data into the octal latches. Pins 3
through 20 are the individual clocks for each octal latch.
4.4 DISPLAY CIRCUIT
The display data is routed from the VIA on PA0 through PA7
by way of connector PlOlO. The data is updated at a 1kHz
rate which means each digit is on for lmsec. Each update
begins by presenting new segment information on the VIA
(I/O) bus (PAO/PA7) and yields a clock pulse on CA2. The
clock pulse inputs to U203 and shifts a digit enable bit to be
enabled. Every eight times the display is updated, a digit
enable bit is generated at PB3 and is routed to the enable data
input of the shift register.
The first four digit drivers drive the rows of the switch matrix.
The switches are arranged in a four by six matrix. The seg-
ment drivers are Q201 through Q208. In addition to driving
the various segments, they also activate the appropriate
LEDs.
4.5 IEEE-488 INTERFACE CIRCUITRY
The IEEE-488 interface circuitry is comprised of GPIB adapter
UlO2, GPIB octal transceivers UlOl, U113 and associated
capacitors. The standard bus connector (J1002) is located on
the rear panel. The primary address is set from front panel
Program 3. There are no primary address dip switches. Refer
to paragraph 2.9.4 for complete details concerning the
primary address.
GPIB adapter U102 is the heart of the IEEE-488 interface cir-
cuitry. U102 is capable of performing all IEEE-488 talk/listen
protocols. The data bus consists of DO through D7. The ad-
dress lines that are routed to the IEEE-488 circuitry are AO, Al
and A2. The REN, IFC, NDAC, NRFD, DAV, EOI, ATN and
SRQ lines are controlled by U102. Before the data is transmit-
ted to the IEEE-488 bus via connector 31002, it is buffered by
the octal bus transceivers U101 and U113. The REN, IFC, EOI
(etc.) lines are buffered by U113. UlOl and U113 operate on
the tri-state output principle. That is, the output is either
high, low or in a high impedance state.