Table of Contents
Advertisement
5.5.6 Interconnect
Board Checks
Check the interconnect board per Table 5-8.
5.6 BAlTERY
CHARGE
The battery backed up functions (Time, Date, Interval, etc.)
are powered by BTlOl and its associated circuitry when the
Model 706 is turned off. The retention time of the battery
backed up functions and data is typically one month with the
unit turned off. To fully charge the battery it takes approx-
imately two weeks (8 hours a day) of normal operation.
5.7 SPECIAL
HANDLING
OF STATIC
SENSITIVE
DEVICES
MOS devices are designed to function
at high impedance
levels. Normal static charge can destroy these devices. Table
5-9 lists all the static sensitive devices of the Model 706.
Steps 1 through 7 provide instruction
on how to avoid
damaging these devices.
1. Devices should be handled and transported in protective
containers, antistatic tubes or conductive foam.
2. Use a properly grounded work bench and a grounding
wrist strap.
3. Handle devices by the body only.
4. PC boards must be grounded to bench while inserting
devices.
5. Use antistatic solder removers.
6. Use grounded tip soldering irons.
7. After devices are soldered or inserted into sockets they are
protected and normal handling can resume.
Table 5-9. Model 706 Static Sensitive Devices
Circuit
Keihtley
Designation
Part No.
u103
LSI-54
u105
LSI-2J
U106
706-801-*
u107
706-800-*
U108
LSI-58
u109
LSI-58
u115
IC-177
u117
IC-149
u120
LSI-28
u121
IC-330
u122
c-107
U123
IC-251
U124
IC-102
U127
c-102
u301
IC-130
u303
IC-251
U42l-U438
IC-339
Step I Item/Component
Table 5-8. Interconnect
Board Checks
1 Rewired
Conditions
1 Remarks
-
1.
J1021 through J1030 pins
+6ti
+4%
Interconnect board supply.
17 and 18 referenced to
pins 5 and 6 (analog
common).
2
Program the Model 706 to scan
channels 1 through 10 at a
two second interval rate.
3
U421 pin 2
+4v
*lV
When the mainframe is scan-
+4v
*lV
ning channel 1. Otherwise OV.
4
U421 pin 5
When the mainframe is scan-
ning channel 2. Otherwise OV.
5
U421 pin 6
+4v
*lV
When the mainframe is scan-
ning channel 3. Otherwise, OV.
6
U421 pin 9
+4v
&lV
When the mainframe is scan-
ning channel 4 Otherwise, OV.
7
U421 pin 12
+4v
+lV
When the mainframe is scan-
ning channel 5. Otherwise, OV.
8
U421 pin 15
+4v
flV
,
When the mainframe is scan-
ning channel 6. Otherwise, OV
9
U421 pin 16
+4v
*lV
When the mainframe is scan-
ning channel 7. Otherwise, OV.
10
U421 pin 19
+4v
flV
When the mainframe is scan-
ning channel 8. Otherwise, OV.
11
U422 pin 2
+4v
*lV
When the mainframe is scan-
ning channel 9. Otherwise, OV.
12
U422 pin 5
+4v
*lV
*
When the mainframe is scan-
ning channel 10. Otherwise, OV.
NOTE
All the steps in Table 5-8 are referenced to Analog Common.
5-8
Advertisement
Table of Contents
