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SECTION 4
THEORY OF OPERATION
4.1 INTRODUCTION
This section
contains
circuit
descriptions
of the Model
705.
The information
is arranged
to provide
a description
of in-
dividual
functional
circuit blocks.
To facilitate
understanding,
the descriptions
are referenced
to Figure
4-1, which
is an
overall block diagram of the Model 705. Detailed schematics
of
the Model 705 are located
in Section
6.
4.2 POWER
SUPPLY
To aid in the understanding
of the following
discussion,
refer
to the block
diagram
in Figure 4-1 and schematic
diagram
705-106 sheet 1 of 3.
The power supply is a conventional
AC to DC power
conver-
ter. Transformer
TlOl
has two
secondaries
that
are wired
together
in series. CR101 is the traditional
bridge rectifier
and
the output
of CR101 is filtered by Cl06 and then fed to VRlOl,
VR102
is a 3-terminal
voltage
regulator
that outputs
a well
regulated
+ 5V supply.
Battery
BTlOl
is a 3.6V Nicad battery
that is used to back up
certain features of the Model 705 (date, time, etc). 0101, 0102
and associated
circuitry are configured
to provide further
filter-
ing. VR103 is a 3-terminal
voltage
regulator
that outputs
a well
regulated
+ 6V. The + 6V supply exclusively
powers
the plug
in scanner
cards,
4.3 MICROCOMPUTER
To simplify
understanding
of the following
discussion
refer to
the
block
diagram
in Figure
4-l
and
schematic
diagram
705-106 sheet 3 of 3.
The
microcomputer
includes
a 6808
microprocessing
unit
U120, a 6522 versatile
interface
adapter
(VIA) U119, a 2732
and 2764
ROMs U122 and U123.
The microcomputer
also
consists
of two
2114
RAMS
U124
and
U125
an address
decoder
U112 (LS138) an asynchronous
communication
inter-
face adapter (ACIA) U118 and assorted buffers and line drivers
U117, U105, U106, UllO,
Ulll,
U116, U126 and U127. The
IEEE-488 interface
circuitry
consists
of a 59914 general
pur-
pose interface
bus adapter
U107, a 75161 general purpose
in-
terface bus transceiver
U108 and a 75160 general purpose
bus
transceiver.
The memory
used in this system is shown
in the
memory
map Figure 4-2. Using address
lines A13,
Al4
and
~15,
U112
sections
the
64k
of
memory
space into
8k
segments.
Interfacing
of the microprocessor
with the RAMS,
ROMs, Front Panel, VIA, ACIA or IEEE-488 interface
circuitry
is controlled
by the address decoder,
U112.
Partial address decoding
is used in this system.
The function
selected
is determined
by the state of the A13, Al4
and Al5
address lines, These address
lines determine
which
output
is
selected by the decoder
U112 in accordance
with the memory
map. Only one of these devices (RAM,
ROM, VIA, ACIA etc.)
will have access to the data bus at any time.
The address
decoder
selects one of the devices
only after a valid memory
address
(VMA)
has been asserted
at the decoders
input
Gl
(pin 6). The VMA
signal
is generated
by the 6808
micro-
processor.
MEMORY
PART
4;
DHsExss
0000
r------
2114
1FFF
2603
EXPANSION
2732
- -
-
3FU
4000
FOR
ACIA
6FFF
DAISY
CHAIN
----
6000
l-----4
I/O,
TIMER
VIA
7FFF
-- -
-
8000
c
IEEE
9914
9FFF
----
A000
1
SWITCH
PORT
1 74LS244
BFFF
_---
coo0
2764
DFFF
__--
EOOO
2732
FFFF .j
Figure 4-2. Memory
Map
Timing
for the computing
sequences
is provided
by 4MHz
crystal Y102. The 6808 microprocessor
divides this signal by
four to produce
a 1 MHz signal at the E (pin 37) output.
This is
a single phase, TTL compatible
clock. The clock may be condi-
tioned by a memory
read signal. This output
is capable of driv-
ing one standard
TTL load and 13OpF.
U103 A, B, C and D, CR102, CR103 and associated
circuitry
form a reset network
which
resets the microprocessor,
VIA,
ACIA and IEEE-488 interface,
The circuit actuates
in the event
the front panel display is not updated
after a specific period of
time (e.g. interval
time) has elapsed due to a lost program
or
power
line transient.
As seen in schematic
705-106 sheet 3 of 3, the data lines runn-
ing throughout
the microcomputer
circuitry
are labled as DO
through
D7. The address lines running
throughout
the micro-
computer
circuitry
are labled as A0 through
A15.
4-1
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