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AMD K6-2E+ manual available for free PDF download: Application Note
AMD K6-2E+ Application Note (98 pages)
Embedded AMD-K6 Processors BIOS Design Guide
Brand:
AMD
| Category:
Computer Hardware
| Size: 1.4 MB
Table of Contents
Table of Contents
3
Revision History
11
Introduction
13
Audience
13
Processor Models and Steppings
14
AMD-K6™E Embedded Processor
15
AMD-K6™-2 Processor
15
AMD-K6™-2E Embedded Processor
16
AMD-K6™-III Processor
17
AMD-K6™-IIIE+ Embedded Processor
17
BIOS Consideration Checklist
18
Cpuid
18
CPU Speed Detection
18
Model-Specific Registers (Msrs)
18
Cache Testing
19
SMM Issues
19
States after RESET and INIT
20
Register States after RESET and INIT
20
AMD-K6™E Processor (Model 7) and AMD-K6™ Processor (Model 8/[7:0]) State after RESET
20
AMD-K6™ Processor (Model 8/[F:8]) and AMD-K6™-2E Processor (Model 8/[F:8]) State after RESET
20
Processor State after INIT
21
AMD-K6™-2E+ (Model D), AMD-K6™-III (Model 9), and AMD-K6™-IIIE+ Processors (Model D)
21
Built-In Self-Test (BIST)
22
CPUID Identification Algorithms
23
Recommended Boot Strings for AMD-K6™ Processors
23
Figure 1. CPUID Instruction Flow Chart
24
System Management Mode (SMM)
25
State-Save Map Differences
25
I/O Trap Dword Differences
25
AMD-K6™ Processor I/O Trap Dword Configuration at Offset Ffa4H
25
Model-Specific Registers Overview
26
Summary by Register of MSR Differences Within the AMD-K6™ Family
26
Summary by Model of MSR Differences Within the
27
Standard Model-Specific Registers (All Models)
28
Model 7 and Model 8/[7:0] Registers
29
Model-Specific Registers Supported by Models 7 and
29
Extended Feature Enable Register (EFER)
30
Figure 2. Extended Feature Enable Register (EFER)
30
Table 10. Extended Feature Enable Register (EFER) Definition
30
Write Handling Control Register (WHCR)
31
Figure 3. Write Handling Control Register (WHCR)
32
SYSCALL/SYSRET Target Address Register (STAR)
34
Figure 4. SYSCALL/SYSRET Target Address Register (STAR)
34
Table 11. SYSCALL/SYSRET Target Address Register (STAR) Definition (Models 8, 9, and D)
34
Model 8/[F:8] Registers
35
(Model 8/[F:8])
35
Table 12. Model-Specific Registers Supported by Model 8/[F:8]
35
Extended Feature Enable Register (EFER)
36
Figure 5. Extended Feature Enable Register (EFER)
36
Table 13. Extended Feature Enable Register (EFER) Definition (Model 8/[F:8])
36
Table 14. Write Ordering and Performance Settings for EFER
38
Write Handling Control Register (WHCR)
39
Figure 6. Write Handling Control Register (WHCR)
40
UC/WC Cacheability Control Register (UWCCR)
42
Figure 7. UC/WC Cacheability Control Register (UWCCR)
43
Table 15. WC/UC Memory Type for UWCCR Register
43
Table 16. Valid Masks and Range Sizes for UWCCR Register
44
Figure 8. Processor State Observability Register (PSOR) (Models 8/[F:8], 9, and Standard-Power D)
46
Processor State Observability Register (PSOR)
46
Table 17. Processor-To-Bus Clock Ratios (Models 8/[F:8] and 9)
47
Table 18. Processor-To-Bus Clock Ratios (Model Standard-Power D)
47
Figure 9. Page Flush/Invalidate Register (PFIR)
48
Page Flush/Invalidate Register (PFIR)
48
Model 9 Registers
50
Table 19. Model-Specific Registers Supported by Model 9
50
Extended Feature Enable Register (EFER)
51
Figure 10. Extended Feature Enable Register (EFER)
51
Table 20. Extended Feature Enable Register (EFER) Definition
51
Figure 11. L2 Cache Organization (AMD-K6™-III Processor)
52
Level-2 Cache Array Access Register (L2AAR)
52
Figure 12. L2 Cache Sector and Line Organization
53
Figure 13. L2 Tag or Data Location
53
Figure 14. L2 Data-EAX
54
Table 21. Tag Versus Data Selector
54
Figure 15. L2 Tag Information (AMD-K6™-III Processor)-EAX
55
Figure 16. LRU Byte
55
Model D Registers
57
Table 22. Model-Specific Registers Supported by Model D
57
Figure 17. Processor State Observability Register (PSOR) (Model D Low-Power Versions)
58
Processor State Observability Register (PSOR) (Low-Power Versions)
58
Table 23. Processor-To-Bus Clock Ratios (Low-Power Model D)
59
Figure 18. L2 Cache Organization
60
Level-2 Cache Array Access Register (L2AAR)
60
Figure 19. L2 Cache Sector and Line Organization
61
Figure 21. L2 Tag or Data Location
62
Figure 22. L2 Data-EAX (same as Figure 14)
63
Table 24. Tag Versus Data Selector (same as Table 21)
63
Figure 23. L2 Tag Information
64
Figure 24. L2 Tag Information
64
Figure 25. LRU Byte (same as Figure 16)
65
Enhanced Power Management Register (EPMR) (Low-Power Versions)
66
Figure 26. Enhanced Power Management Register (EPMR)
66
Table 25. Enhanced Power Management Register (EPMR) Definition (Low-Power Model D)
66
EPM 16-Byte I/O Block (Low-Power Versions Only)
67
Figure 27. EPM 16-Byte I/O Block (Low-Power Model D)
67
Table 26. EPM 16-Byte I/O Block Definition (Low-Power Model D)
67
Figure 28. Bus Divisor and Voltage ID Control (BVC) Field
68
Table 27. Bus Divisor and Voltage ID Control (BVC) Definition
68
Embedded AMD Processor Recognition
69
CPUID Instruction Overview
69
Testing for the CPUID Instruction
70
Using CPUID Functions
71
Identifying the Processor's Vendor
72
Table 28. CPUID Functions in AMD-K6™ Processors
72
Testing for Extended Functions
73
Determining the Processor Signature
73
Figure 29. Contents of EAX Register Returned by Function 1
74
Table 29. Processor Signatures for AMD-K6™ Processors
74
Identifying Supported Features
75
Table 30. Standard and Extended Feature Bits
75
Determining Instruction Set Support
76
Support
77
AMD Processor Signature (Extended Function)
78
Displaying the Processor's Name
78
Figure 30. Contents of EAX Register Returned by Extended Function 8000_0001H
78
Displaying Cache Information
79
Determining AMD Powernow!™ Technology Information
79
Sample Code
79
New AMD-K6™ Processor Instructions
80
Additional Considerations
81
Software Timing Dependencies Relative to Memory Controller Setup
81
Pipelining Support
81
Read-Only Memory
82
Appendix A
83
Cpuid
83
Standard Functions
84
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0—November
85
Table 31. Standard Feature Flag Descriptions
86
Extended Functions
87
Table 32. Extended Feature Flag Descriptions
88
Table 33. EBX Format Returned by Function 8000_0005H
90
Table 34. ECX Format Returned by Function 8000_0005H
90
Table 35. EDX Format Returned by Function 8000_0005H
90
Table 36. ECX Format Returned by Function 8000_0006H
91
Table 37. EDX Format Returned by Function 8000_0007H
91
Cache Associativity Field Definitions
92
Table 38. Associativity Values for L2 Cache
92
Appendix B
93
Values Returned by the CPUID Instruction
93
Table 39. CPUID Values Returned by AMD-K6™ Processors
93
Index
95
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