Sun Microsystems Ultra 24 Service Manual page 126

BIOS Port 80 POST Codes (Continued)
TABLE B-1
Post Code Description
08h 1. Test special keyboard controller for Winbond 977 series Super I/O
2. Enable keyboard interface.
09h Reserved.
0Ah 1. Disable PS/2 mouse interface (optional).
2. Auto detect ports for keyboard and mouse followed by a port and
3. Reset keyboard for Winbond 977 series Super I/O chips.
0Bh Reserved.
0Ch Reserved.
0Dh Reserved.
0Eh Test F000h segment shadow to see whether it is read/writable or
not. If test fails, keep beeping the speaker.
0Fh Reserved.
10h Autodetect flash type to load appropriate flash R/W codes into the
runtime area in F000 for ESCD & DMI support.
11h Reserved.
12h Use walking 1's algorithm to check out interface in CMOS circuitry.
Also, set real-time clock power status, and then check for override.
13h Reserved.
14h Program chipset default values into chipset. Chipset default values
are MODBINable by OEM customers.
15h Reserved.
16h Initial onboard clock generator if Early_Init_Onboard_Generator is
defined. See also POST 26h.
17h Reserved.
18h Detect CPU information including brand, SMI type (Cyrix or Intel),
and CPU level (586 or 686).
19h Reserved.
1Ah Reserved.
1Bh Initial interrupts vector table. All hardware interrupts are directed to
SPURIOUS_INT_HDLR and software interrupts to
SPURIOUS_soft_HDLR.
1Ch Reserved.
1Dh Initial EARLY_PM_INIT switch.
chips.
interface swap (optional).
Appendix B BIOS POST Codes B-3