Link Interface Timing; Eeprom Interface - Intel 82540EP Datasheet

82540EP — Networking Silicon
4.5.2

Link Interface Timing

Table 17. Rise and Fall Times
Symbol
TR
TF
TR
TF
Figure 9. Link Interface Rise/Fall Timing
4.5.3

EEPROM Interface

Table 18. Link Interface Clock Requirements
Symbol
TPW
a. The EEPROM clock is derived from a 125 MHz internal clock.
Table 19. Link Interface Clock Requirements
Symbol
TDOS
TDOH
a.
T h e E E _ D O s e t u p a n d h o l d t i m e i s a f u n c t i o n o f t h e P C I b u s C L K c y c l e t i m e b u t i s r e f e r e n c e d t o O _ E E _ S K .
26
Parameter
Clock rise time
Clock fall time
Data rise time
Data fall time
2.0 V
0.8 V
Parameter
EE_SK pulse width
a
Parameter
EE_DO setup time
EE_DO hold time
Condition Min
0.8 V to 2.0 V 0.7
2.0 V to 0.8 V 0.7
0.8 to 2.0 V 0.7
2.0 V to 0.8 V 0.7
T T
R F
Min Typ
TPERIOD
Min Typ
TCYC*2
0
Max Unit
ns
ns
ns
ns
Max Unit
*128 ns
Max Unit
ns
ns
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