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4.5.1.2
PCI Bus Interface Timing
Table 15. PCI Bus Interface Timing Parameters
Symbol
TVAL
TVAL(ptp)
TON
TOFF
TSU
TSU(ptp)
TH
TRRSU
TRRH
NOTES:
1. Output timing measurements are as shown.
2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than
bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed.
3. Input timing measurements are as shown.
Figure 3. PCI Bus Interface Output Timing Measurement
Datasheet
Parameter
CLK to signal valid delay: bussed
signals
CLK to signal valid delay: point-
to-point signals
Float to active delay
Active to float delay
Input setup time to CLK: bussed
signals
Input setup time to CLK: point-to-
point signals
Input hold time from CLK
REQ64# to RST# setup time
RST# to REQ64# hold time
PCI_CLK
Output
Delay
Tri-State
Output
Networking Silicon — 82540EP
PCI 66MHz
Min
Max
2
6
2
6
2
14
3
5
0
10*
TCYC
0
V
TEST
V
V
output current
leakage current
T
ON
T
OFF
PCI 33 MHz
Units
Min
Max
2
11
ns
2
12
ns
2
ns
28
ns
7
ns
10, 12
ns
0
ns
10*
ns
TCYC
0
ns
V
TH
V
TL
TEST
(3.3V Signalling)
STEP
23
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